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| 型號： | MB81V18160A-70 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 1M ×16 BIT Fast Page Mode Dynamic RAM(CMOS 1M ×16 位快速頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS 100萬× 16位快速頁面模式動態(tài)RAM的CMOS（100萬× 16位快速頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 21/25頁 |
| 文件大小： | 579K |
| 代理商： | MB81V18160A-70 |
21
MB81V18160A-60/60L/-70/70L
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—
—
—
DESCRIPTION
A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the function
of CAS-before-RAS refresh circuitry. If a CAS-before-RAS refresh cycle CAS makes a transition from High to Low while RAS is held
Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows:
Row Address: Bits A
0
through A
9
are defined by the on-chip refresh counter
Column Addresses: Bits A
0
through A
9
are defined by latching levels on A
0
to A
9
at the second falling edge of CAS.
The CAS-before-RAS Counter Test procedure is as follows;
1) Initialize the internal refresh address counter by using 8 RAS-only refresh cycles.
2) Use the same column address throughout the test.
3) Write “0” to all 1,024 row addresses at the same column address by using normal write cycles.
4) Read “0” written in procedure 3) and check; simultaneously write “1” to the same addresses by using CAS-before-RAS
refresh counter test (read-modify-write cycles). Repeat this procedure 1,024 times with addresses generated by the internal
refresh address counter.
5) Read and check data written in procedure 4) by using normal read cycle for all 1,024 memory locations.
6) Reverse test data and repeat procedures 3), 4), and 5).
(At recommended operating conditions unless otherwise noted.)
Fig. 16 – CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
RAS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
A
0
to A
9
WE
V
IH
V
IL
V
OH
V
OL
DQ
(Input)
V
IH
V
IL
OE
V
IH
V
IL
t
CSR
DQ
(Output)
t
RP
t
CP
t
RCS
t
FCAH
t
ASC
t
WP
t
CHR
t
FRSH
t
RWL
t
FCWD
t
DH
t
DS
t
DZC
t
OED
t
ON
t
OEA
t
DZO
t
OEZ
t
OEH
VALID DATA IN
HIGH-Z
COLUMN ADDRESSES
LCAS
or
UCAS
t
FCAC
HIGH-Z
HIGH-Z
t
FCAS
t
CWL
Valid Data
“H” or “L” level (excluding Address and DQ)
“H” or “L” level, “H”
→
“L” or “L”
→
“H” transition (Address and DQ)
MB81V18160A-70/70L
Min
.
—
MB81V18160A-60/60L
Min.
—
Unit
Parameter
Max.
55
ns
ns
ns
ns
ns
No
.
Max.
50
—
—
—
—
90
91
92
93
94
Symbol
CAS to WE Delay Time
CAS Pulse Width
RAS Hold Time
35
77
99
99
35
70
90
90
Column Address Hold Time
Access Time from CAS
t
FCAC
t
FCAH
t
FCWD
t
FCAS
t
FRSH
Note:
Assumes that CAS-before-RAS refresh counter test cycle only.
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