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參數(shù)資料
| 型號： | MB81V18165A-70L |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 1M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×16位超級頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS 100萬× 16位的超頁模式動態(tài)RAM的CMOS（100萬× 16位超級頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/30頁 |
| 文件大?。?/td> | 681K |
| 代理商： | MB81V18165A-70L |
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1
DS05-10193-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS
1 M
×
16 BITS
HYPER PAGE MODE DYNAMIC RAM
MB81V18165A-60/60L/-70/70L
CMOS 1,048,576
×
16 BITS Hyper Page Mode Dynamic RAM
I
DESCRIPTION
The Fujitsu MB81V18165A is a fully decoded CMOS Dynamic RAM (DRAM) that contains 16,777,216 memory
cells accessible in 16-bit increments. The MB81V18165A features a “hyper page” mode of operation whereby
high-speed random access of up to 1,024
×
16 bits of data within the same row can be selected. The
MB81V18165A DRAM is ideally suited for mainframe, buffers, hand-held computers video imaging equipment,
and other memory applications where very low power dissipation and high bandwidth are basic requirements of
the design. Since the standby current of the MB81V18165A is very small, the device can be used as a non-
volatile memory in equipment that uses batteries for primary and/or auxiliary power.
The MB81V18165A is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon and two-
layer aluminum process. This process, coupled with advanced stacked capacitor memory cells, reduces the
possibility of soft errors and extends the time interval between memory refreshes. Clock timing requirements for
the MB81V18165A are not critical and all inputs are LVTTL compatible.
I
PRODUCT LINE & FEATURES
Parameter
MB81V18165A
-60L
-60
-70
-70L
RAS Access Time
Random Cycle Time
Address Access Time
CAS Access Time
Hyper Page Mode Cycle Time
60 ns max.
104 ns min.
30 ns max.
15 ns max.
25 ns min.
648 mW max.
70 ns max.
124 ns min.
35 ns max.
17 ns max.
30 ns min.
612 mW max.
Low Power
Dissipation
Operating Current
Standby
Current
LVTTL Level
CMOS Level
3.6 mW max.
1.8 mW max.
3.6 mW max.
0.54 mW max.
3.6 mW max.
1.8 mW max.
3.6 mW max.
0.54 mW max.
1,048,576 words
×
16 bits organization
Silicon gate, CMOS, Advanced Stacked
Capacitor Cell
All input and output are LVTTL compatible
1,024 refresh cycles every 16.4 ms
Self refresh function
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
Standard and low power versions
Early write or OE controlled write capability
RAS-only, CAS-before-RAS, or Hidden Refresh
Hyper page Mode, Read-Modify-Write capability
On chip substrate bias generator for high
performance
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| MB81V18165B-50 | 1 M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1 M ×16位超級頁面存取模式動態(tài)RAM) |
| MB81V18165B-60 | 1 M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1 M ×16位超級頁面存取模式動態(tài)RAM) |
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| MB81V4260S-60 | CMOS 256K ×16 BIT FAST PAGE MODE DYNAMIC RAM(CMOS 256K ×16 位快速頁面存取模式動態(tài)RAM) |
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