參數(shù)資料
型號: MB81V18165B-50
廠商: Fujitsu Limited
英文描述: 1 M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1 M ×16位超級頁面存取模式動態(tài)RAM)
中文描述: 1米× 16位的超頁模式動態(tài)RAM的CMOS(1米× 16位超級頁面存取模式動態(tài)內(nèi)存)
文件頁數(shù): 20/29頁
文件大?。?/td> 583K
代理商: MB81V18165B-50
20
MB81V18165B-50/-60
LCAS
or
UCAS
V
IH
V
IL
t
DH
t
CAS
t
CP
t
RASP
t
RP
ROW
ADD
t
RSH
t
HPC
t
RCD
t
CSH
t
CAS
t
ASC
t
CAH
COL
ADD
COL
ADD
HIGH-Z
t
CAS
COL
ADD
t
CAH
t
RAL
t
ASC
t
CAH
VALID
DATA
VALID
DATA
VALID
DATA
t
WCS
t
WCH
t
WCS
t
WCH
t
WCS
t
WCH
t
DS
t
DH
t
ASC
t
DS
t
DH
t
DS
t
AR
t
WCR
t
DHR
t
RHCP
During one cycle is achieved, the input/output timing apply the same manner as the former cycle.
t
CWL
t
RWL
t
CWL
t
CRP
t
ASR
t
RAH
DESCRIPTION
The hyper page mode early write cycle is executed in the same manner as the hyper page mode read cycle except the states of
WE and OE are reversed. Data appearing on the DQ
1
to DQ
8
is latched on the falling edge of LCAS and one appearing on the
DQ
9
to DQ
16
is latched on the falling edge of UCAS and the data is written into the memory. During the hyper page mode early
write cycle, including the delayed (OE) write and read-modify-write cycles, t
CWL
must be satisfied.
Fig. 12 – HYPER PAGE MODE EARLY WRITE CYCLE
“H” or “L” level (excluding Address and DQ)
“H” or “L” level, “H”
“L” or “L”
“H” transition (Address and DQ)
A
0
to A
9
V
IH
V
IL
RAS
V
IH
V
IL
WE
V
IH
V
IL
DQ
(Output)
V
OH
V
OL
DQ
(Input)
V
IH
V
IL
t
CWL
相關(guān)PDF資料
PDF描述
MB81V18165B-60 1 M ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 1 M ×16位超級頁面存取模式動態(tài)RAM)
MB81V4100C-60 CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1 位快速頁面存取模式動態(tài)RAM)
MB81V4100C-70 CMOS 4 M ×1 BIT Fast Page Mode DRAM(CMOS 4 M ×1 位快速頁面存取模式動態(tài)RAM)
MB81V4260S-60 CMOS 256K ×16 BIT FAST PAGE MODE DYNAMIC RAM(CMOS 256K ×16 位快速頁面存取模式動態(tài)RAM)
MB81V4260S-70 CMOS 256K ×16 BIT FAST PAGE MODE DYNAMIC RAM(CMOS 256K ×16 位快速頁面存取模式動態(tài)RAM)
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