- 您現(xiàn)在的位置：買賣IC網 > PDF目錄377886 > MB81V4265S-70 (Fujitsu Limited) CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16位超級頁面存取模式動態(tài)RAM) PDF資料下載
參數資料
| 型號： | MB81V4265S-70 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 256K ×16 BIT Hyper Page Mode Dynamic RAM(CMOS 256K ×16位超級頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS 256K × 16位的超頁模式動態(tài)RAM的CMOS（256K × 16位超級頁面存取模式動態(tài)內存） |
| 文件頁數： | 26/29頁 |
| 文件大?。?/td> | 377K |
| 代理商： | MB81V4265S-70 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當前第26頁第27頁第28頁第29頁
26
MB81V4265S-60/-70
LCAS
or
UCAS
Fig. 20 – SELF REFRESH CYCLE (A0-A8 = WE = OE = “H” or “L”)
(At recommended operating conditions unless otherwise noted.)
MB81V4265S-60
Note:
Assumes Self Refresh cycle only.
Parameter
Unit
Min.
100
119
–50
Max.
—
No.
Min.
100
104
–50
Max.
—
74
75
Symbol
—
76
—
RAS Pulse Width
RAS Precharge Time
CAS Hold Time
MB81V4265S-70
t
RASS
t
RPS
t
CHS
DESCRIPTION
The self refresh cycle provides a refresh operation without external clock and external Address. Self Refresh control circuit on chip
is operated in the Self Refresh cycle and refresh operation can be automatically executed using internal refresh address counter
and timing generator.
If CAS goes to “L” before RAS goes to “L” (CBR) and the condition of CAS “L” and RAS “L” is kept for term of t
RASS
(more than
100
μ
s), the device can enter the self refresh cycle. Following that, refresh operation is automatically executed at fixed intervals
using internal refresh address counter during “RAS=L” and “CAS=L”.
Exit from Self Refresh cycle is performed by toggling RAS and CAS to “H” with specified t
CHS
min. In this time, RAS must be kept
“H” with specified t
RPS
min.
Using self refresh mode, data can be retained without external CAS signal during system is in standby.
Restriction for Self Refresh operation
For Self Refresh operation, the notice below must be considered.
1) In the case that distributed CBR refresh are operated between read/write cycles
Self Refresh cycles can be executed without special rule if 512 cycles of distributed CBR refresh are executed
within t
REF
max.
2) In the case that burst CBR refresh or distributed/burst RAS-only refresh are operated between read/write
cycles 512 times of burst CBR refresh or 512 times of burst RAS-only refresh must be executed before and
after Self refresh cycles.
V
IH
V
IL
RAS
“H” or “L”
V
IH
V
IL
RAS
V
IH
V
IL
V
OH
V
OL
DQ
(output)
t
NS
< 0.5 ms
512 burst refresh cycle
Read/Write operation
512 burst refresh cycle
Self Refresh operation
t
RASS
Read/Write operation
t
SN
< 0.5 ms
HIGH-Z
t
RASS
t
RPS
t
RPC
t
CHS
t
CHR
t
CPN
t
OFF
t
OH
* Read/Write operation can be performed non refresh time within t
NS
or t
SN
μ
s
ns
ns
—
—
*
相關PDF資料 |
PDF描述 |
|---|---|
| MB81V4400C-60 | CMOS 1M x 4 Bit Fast Page Mode Dynamic RAM(CMOS 1M x 4位快速頁模式動態(tài)RAM) |
| MB81V4400C-70 | CMOS 1M x 4 Bit Fast Page Mode Dynamic RAM(CMOS 1M x 4位快速頁模式動態(tài)RAM) |
| MB81V4405C-60 | CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動態(tài)RAM) |
| MB81V4405C-70 | CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動態(tài)RAM) |
| MB81V4800S-60 | CMOS 512K×8 BIT Fast Page Mode DRAM(CMOS 512K×8位快速頁面存取模式動態(tài)RAM) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MB82 | 功能描述:RECTIFIER BRIDGE 8A 200V BR-6 RoHS:否 類別:分離式半導體產品 >> 橋式整流器 系列:- 產品變化通告:Product Discontinuation 14/Mar/2011 標準包裝:1,500 系列:- 電壓 - 峰值反向(最大):1000V 電流 - DC 正向(If):1.5A 二極管類型:單相 速度:標準恢復 >500ns，> 200mA（Io） 反向恢復時間(trr):- 安裝類型:表面貼裝 封裝/外殼:4-SMD 包裝:帶卷 (TR) 供應商設備封裝:4-SDIP |
| MB820 | 功能描述:ACCY MOUNT BMM 3/4 58A RoHS:是 類別:RF/IF 和 RFID >> RF配件 系列:* 標準包裝:1 系列:* |
| MB-8210 | 制造商:Maxxtro 功能描述:Bulk |
| MB82101BAN | 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
| MB82101BBN | 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
發(fā)布緊急采購，3分鐘左右您將得到回復。