- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377886 > MB81V4405C-70 (Fujitsu Limited) CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動態(tài)RAM) PDF資料下載
參數(shù)資料
| 型號： | MB81V4405C-70 |
| 廠商： | Fujitsu Limited |
| 英文描述： | CMOS 1M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 1M ×4 位超級頁面存取模式動態(tài)RAM) |
| 中文描述： | 的CMOS 100萬× 4位超頁模式動態(tài)RAM的CMOS（100萬× 4位超級頁面存取模式動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 5/30頁 |
| 文件大?。?/td> | 348K |
| 代理商： | MB81V4405C-70 |
第1頁第2頁第3頁第4頁當前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁
5
MB81V4405C-60/MB81V4405C-70
I
RECOMMENDED OPERATING CONDITIONS
* :Undershoots of up to –2.0 volts with a pulse width not exceeding 20 ns are acceptable.
I
ADDRESS INPUTS
Twenty input bits are required to decode any four of 4,194,304 cell addresses in the memory matrix. Since only ten
address bits are available, the column and row inputs are separately strobed by CAS and RAS as shown in Figure
5. First, ten row address bits are input on pins A
0
-through-A
ten column address bits are input and latched with the column address strobe (CAS). Both row and column ad-
dresses must be stable on or before the falling edge of CAS and RAS, respectively. The address latches are of the
flow-through type; thus, address information appearing after t
address.
WRITE ENABLE
The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated;
when WE is High, a read cycle is selected. During the read mode, input data is ignored.
DATA INPUT
Input data is written into memory in either of three basic ways—an early write cycle, an OE (delayed) write cycle,
and a read-modify-write cycle. The falling edge of WE or CAS, whichever is later, serves as the input data-latch
strobe. In an early write cycle, the input data (DQ
1
-DQ
4
) is strobed by CAS and the setup/hold times are referenced
to CAS because WE goes Low before CAS. In a delayed write or a read-modify-write cycle, WE goes Low after
CAS; thus, input data is strobed by WE and all setup/hold times are referenced to the write-enable signal.
DATA OUTPUT
The three-state buffers are LVTTL compatible with a fanout of one TTL loads. Polarity of the output data is identical
to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes
Low. When a read or read-modify-write cycle is executed, valid outputs and High-Z state are obtained under the
following conditions:
t
RAC
:
from the falling edge of RAS when t
RCD
(max.) is satisfied.
t
CAC
:
from the falling edge of CAS when t
RCD
is greater than t
t
AA
:
from column address input when t
RAD
is greater than t
t
OEA
:
from the falling edge of OE when OE is brought Low after t
t
OEZ
:
from OE inactive.
t
OFF
:
from CAS inactive while RAS inactive.
t
OFR
:
from RAS inactive while CAS inactive.
t
WEZ
:
from WE active while CAS inactive.
The data remains valid after either OE is inactive, or both RAS and CAS are inactive, or CAS is reactived. When
an early write is executed, the output buffers remain in a high-impedance state during the entire cycle.
FUNCTIONAL OPERATION
9
and latched with the row address strobe (RAS) then,
RAH
(min.) + t
T
is automatically treated as the column
RCD
(max.), and t
, t
(max.).
RAD
RCD
(max.) is satisfied.
.
RAC
CAC
, or t
AA
Parameter
Notes
Symbol
Min.
Typ.
Max.
Unit
Ambient
Operating Temp.
Supply Voltage
V
CC
3.0
3.3
3.6
V
0
°
C to +70
°
C
V
SS
0
0
0
Input High Voltage, all inputs
V
IH
2.0
—
V
CC
+0.3
V
Input Low Voltage, all inputs*
V
IL
–0.3
—
0.8
V
1
1
1
相關PDF資料 |
PDF描述 |
|---|---|
| MB81V4800S-60 | CMOS 512K×8 BIT Fast Page Mode DRAM(CMOS 512K×8位快速頁面存取模式動態(tài)RAM) |
| MB81V4800S-70 | CMOS 512K×8 BIT Fast Page Mode DRAM(CMOS 512K×8位快速頁面存取模式動態(tài)RAM) |
| MB8431-12L | 2K x 8 Bits CMOS Dual-Port Static Random Access |
| MB8431 | 2K x 8 Bits CMOS Dual-Port Static Random Access |
| MB8431-12 | 2K x 8 Bits CMOS Dual-Port Static Random Access |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MB82 | 功能描述:RECTIFIER BRIDGE 8A 200V BR-6 RoHS:否 類別:分離式半導體產(chǎn)品 >> 橋式整流器 系列:- 產(chǎn)品變化通告:Product Discontinuation 14/Mar/2011 標準包裝:1,500 系列:- 電壓 - 峰值反向(最大):1000V 電流 - DC 正向(If):1.5A 二極管類型:單相 速度:標準恢復 >500ns，> 200mA（Io） 反向恢復時間(trr):- 安裝類型:表面貼裝 封裝/外殼:4-SMD 包裝:帶卷 (TR) 供應商設備封裝:4-SDIP |
| MB820 | 功能描述:ACCY MOUNT BMM 3/4 58A RoHS:是 類別:RF/IF 和 RFID >> RF配件 系列:* 標準包裝:1 系列:* |
| MB-8210 | 制造商:Maxxtro 功能描述:Bulk |
| MB82101BAN | 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
| MB82101BBN | 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
發(fā)布緊急采購，3分鐘左右您將得到回復。