參數(shù)資料
型號(hào)： MB86977PFV-G-BND
廠商： FUJITSU LTD
元件分類： 通信及網(wǎng)絡(luò)
英文描述： IP PACKET FORWARDING ENGINE
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP208
封裝： PLASTIC, LQFP-208
文件頁(yè)數(shù)： 5/30頁(yè)
文件大?。?/td> 149K
代理商： MB86977PFV-G-BND
MB86977
5
I
PIN DESCRIPTION
Host (SRAM) interface
Pin No.
RMII interface
Pin No.
Note : The logical AND of the TX_EN and CRS_DV signals indicate a collision during half duplex modes.
Pin Name
I/O
Function
173 to 184
A2 to A13
I
ADDRESS BUS
Address input
15 to 25
29 to 38
42 to 52
DQ0 to DQ31
I/O
DATA INPUT/OUTPUT
Data input/output (32 bit)
166
CS_
I
CHIP SELECT
Chip select input
167
WE_
I
WRITE ENABLE
Write operation enable signal (low enable)
168
RE_
I
READ ENABLE
Read operation enable signal (low enable)
8
INT_
O
INTERRUPT
Interrupt indication (low enable)
Pin Name
I/O
Function
164
REF_CLK
I
REFERENCE CLOCK
Reference clock from the PHY device.
The frequency is 50 MHz for both 10 Mbps and 100 Mbps.
150, 151
108, 109
60, 61
102, 103
TXD_W [1 : 0]
TXD_D [1 : 0]
TXD_0 [1 : 0]
TXD_1 [1 : 0]
O
TRANSMIT DATA
The two bit data is transmitted to PHY devices through this
interface. Synchronous with REF_CLK.
149
107
59
101
TX_EN_W
TX_EN_D
TX_EN_0
TX_EN_1
O
TRANSMIT ENABLE
Active high signal indicates that TX data is valid.Synchronous with
REF_CLK.
141
127
79
93
RX_ER_W
RX_ER_D
RX_ER_0
RX_ER_1
I
RECEIVE ERROR
Active high signal indicates that an invalid symbol has been
detected within a received packet.This input is ignored when the
CRS_DV signal is inactive.
137, 138
123, 124
75, 76
89, 90
RXD_W [1 : 0]
RXD_D [1 : 0]
RXD_0 [1 : 0]
RXD_1 [1 : 0]
I
RECEIVE DATA
The two bit data is received from the PHY device through this
interface.
132
118
70
84
CRS_DV_W
CRS_DV_D
CRS_DV_0
CRS_DV_1
I
CARRIER SENSE / RECEIVE DATA VALID
PHY Device inputs active high signal when the interface is
receiving data. Asynchronous assertion/deassertion by PHY
device upon carrier detection/carrier invalid.
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