
3-44 Chapter 3 CPU
MB89190/190A series
3.7 Standby Mode (Low Power Consumption)
3.7.7 Precautions when Using Standby Mode
Even when the standby mode is set in the standby control register (STBC), con-
trol does not transit to the standby mode when an interrupt request occurs from
resource. Also, the operation after control returns to the normal operation state
from the standby mode due to an interrupt depends on whether the interrupt re-
quest is accepted.
T Transition of control to standby mode and interrupt
When an interrupt request occurs from a resource with an interrupt priority higher than 11B to the CPU, 1
is written to the standby control register stop bit (STBC: STP) and the sleep bit (SLP) is ignored, so
control does not transit to the standby mode (control does not transit to standby mode even after interrupt
processing). This does not depend on whether the CPU accepts the interrupt. Even when the CPU is
currently performing interrupt processing, control can be transited to the standby mode when the interrupt
request flag bit is cleared and no other interrupt requests occur.
T Cancellation of standby mode due to interrupt
When an interrupt request with an interrupt priority higher than 11B occurs from a resource during the
sleep or stop mode, the standby mode is cancelled. This does not depend on whether the CPU accepts
the interrupt.
After the cancellation, when as a normal interrupt operation the priority of the interrupt level setting
registers (ILR1 to ILR3) associated with the interrupt request is higher than the condition code register
interrupt level bits (CCR: IL1, 0) and when the interrupt enable flag is set to Enable (CCR: I = 1), control
branches to the interrup-processing routine. When the interrupt is not accepted, operation is resumed
starting with the instruction immediately after the instruction that started the standby mode. To prevent
control branching to the interrupt-processing routine immediately after return, it is necessary to measures
such as disabling the interrupt before setting the standby mode.
T Precautions when setting standby mode
Set either the sleep bit (STBC: SLP) or stop bit (STP) of the standby control register to 1 (When these bits
are set concurrently to 1, a transition is made to the stop mode).
T Oscillation stabilization wait time
In the stop mode, the oscillator for the original oscillation is stopped, so the oscillation stabilization wait
time is required after the oscillator restarts. The oscillation stabilization wait time is an option, and can be
selected by specifying the bit for the oscillation stabilization wait time of the time-base timer counter.
If the time-base timer selected time interval is shorter than the oscillation stabilization wait time, an
interval timer interrupt request occurs during the oscillation stabilization wait time.
To prevent this,
disable the time-base timer interrupt request output as necessary (TBTC: TBIE = 0) before transition of
control to the stop mode.