MB90420G/5G (A) Series
13
s
s HANDLING DEVICES
When handling semiconductor devices, care must be taken with regard to the following ten matters.
Strictly observe maximum rated voltages (prevent latchup)
Stable supply voltage
Power-on procedures
Treatment of unused input pins
Treatment of A/D converter power supply pins
Use of external clock signals
Power supply pins
Proper sequence of A/D converter power supply analog input
Handling the power supply for high-current output buffer pins (DVCC, DVSS)
Pull-up/pull-down resistance
Precautions when not using a sub clock signal.
Precautions for Handling Semiconductor Devices
Strictly observe maximum rated voltages (prevent latchup)
When CMOS integrated circuit devices are subjected to applied voltages higher than VCC at input and output
pins other than medium- and high-withstand voltage pins, or to voltages lower than VSS, or when voltages in
excess of rated levels are applied between VCC and VSS, a phenomenon known as latchup can occur. In a latchup
condition, supply current can increase dramatically and may destroy semiconductor elements. In using semi-
conductor devices, always take sufficient care to avoid exceeding maximum ratings.
Also care must be taken when power to analog systems is switched on or off, to ensure that the analog power
supply (AVCC, AVRH, DVCC) and analog input do not exceed the digital power supply (VCC) .
Once the digital power supply (VCC) is switched on, the analog power (AVCC,AVRH,DVCC) may be turned on in
any sequence.
Stable supply voltage
Even within the warranted operating range of VCC supply voltage, sudden fluctuations in supply voltage can
cause abnormal operation. The recommended stability for ripple fluctuations (P-P values) at commercial fre-
quencies (50 to 60 Hz) should be within 10
% of the standard VCC value, and voltage fluctuations that occur during
switching of power supplies etc. should be limited to transient fluctuation rates of 0.1 V/ms or less.
Power-on procedures
In order to prevent abnormal operation of the internal built-in step-down circuits, voltage rise time during power-
on should be attained within 50
s (0.2 V to 2.7 V) .
Treatment of unused input pins
If unused input pins are left open, they may cause abnormal operation or latchup which may lead to permanent
damage to the semiconductor. Any such pins should be pulled up or pulled down through resistance of at least
2 k
.
Also any unused input/output pins should be left open in output status, or if found set to input status, they should
be treated in the same way as input pins.
Treatment of A/D converter power supply pins
Even if the A/D converter is not used, pins should be connected so that AVCC
= VCC, and AVSS = AVRH = VSS.