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參數(shù)資料
| 型號： | MB90F428GPF |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 51/99頁 |
| 文件大?。?/td> | 1714K |
| 代理商： | MB90F428GPF |
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MB90420G/5G (A) Series
55
13. Low voltage/Program Looping Detection Reset Circuit
The Low voltage detection reset circuit is a function that monitors power supply voltage in order to detect when
a voltage drops below a given voltage level. When a low voltage condition is detected, an internal reset signal
is generated.
The Program Looping detection reset circuit is a count clock with a 20-bit counter that generates an internal
reset signal if not cleared within a given time after startup.
(1) Low voltage detection reset circuit
When a low voltage condition is detected, the low voltage detection flag (LVRC : LVRF) is set to “1” and an
internal reset signal is output.
Because the low voltage detection circuit continues to operate even in stop mode, detection of a low voltage
condition generates an internal reset and releases stop mode.
During an internal RAM write cycle, an internal reset is generated after the completion of writing. During the
output of this internal reset, the reset output from the low voltage detection circuit is suppressed.
(2) Program Looping detection reset circuit
The Program Looping detection reset circuit is a counter that prevents program looping. The counter starts
automatically after a power-on reset, and must be continually cleared within a given time. If the given time interval
elapses and the counter has not been cleared, a cause such as infinite program looping is assumed and an
internal reset signal is generated. The internal reset generated form the Program Looping detection circuit has
a width of 5 machine cycles.
* : This value assumes an oscillation clock speed of 4 MHz.
During recovery from standby mode the detection period is the maximum interval plus 20
s.
This circuit does not operate in modes where CPU operation is stopped.
The Program Looping detection reset circuit counter is cleared under any of the following conditions.
1. Writing “0” to the LVRC register CL bit
2. Internal reset
3. Main oscillation clock stop
4. Transition to sleep mode
5. Transition to time base timer mode or clock mode
6. Start of hold
Detection voltage
4.0 V
± 0.3 V
Interval duration
Number of oscillation clock cycles
Approx. 262 ms *
220 cycles
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