![](http://datasheet.mmic.net.cn/330000/MB90460_datasheet_16437496/MB90460_20.png)
MB90460 Series
20
I
I/O MAP
(Continued)
Address
Abbrevia-
tion
Register
Byte
access
Word
access
Resource
name
Initial value
000000
H
PDR0
Port 0 data register
R/W
R/W
Port 0
XXXXXXXX
B
000001
H
PDR1
Port 1 data register
R/W
R/W
Port 1
XXXXXXXX
B
000002
H
PDR2
Port 2 data register
R/W
R/W
Port 2
XXXXXXXX
B
000003
H
PDR3
Port 3 data register
R/W
R/W
Port 3
XXXXXXXX
B
000004
H
PDR4
Port 4 data register
R/W
R/W
Port 4
-XXXXXXX
B
000005
H
PDR5
Port 5 data register
R/W
R/W
Port 5
XXXXXXXX
B
000006
H
PDR6
Port 6 data register
R/W
R/W
Port 6
----XXXX
B
000007
H
Prohibited area
000008
H
PWCSL0
PWC control status register CH0
R/W
R/W
PWC timer
(CH0)
00000000
B
000009
H
PWCSH0
R/W
R/W
00000000
B
00000A
H
PWC0
PWC data buffer register CH0
R/W
XXXXXXXX
B
00000B
H
XXXXXXXX
B
00000C
H
DIV0
Divide ratio control register CH0
R/W
R/W
------00
B
00000D
H
to 0F
H
Prohibited area
000010
H
DDR0
Port 0 direction register
R/W
R/W
Port 0
00000000
B
000011
H
DDR1
Port 1 direction register
R/W
R/W
Port 1
00000000
B
000012
H
DDR2
Port 2 direction register
R/W
R/W
Port 2
00000000
B
000013
H
DDR3
Port 3 direction register
R/W
R/W
Port 3
00000000
B
000014
H
DDR4
Port 4 direction register
R/W
R/W
Port 4
-0000000
B
000015
H
DDR5
Port 5 direction register
R/W
R/W
Port 5
00000000
B
000016
H
DDR6
Port 6 direction register
R/W
R/W
Port 6
----0000
B
000017
H
ADER
Analog input enable register
R/W
R/W
Port 5, A/D
11111111
B
000018
H
Prohibited area
000019
H
CDCR0
Clock division control register 0
R/W
R/W
Communication
prescaler 0
0---0000
B
00001A
H
Prohibited area
00001B
H
CDCR1
Clock division control register 1
R/W
R/W
Communication
prescaler 1
0---0000
B
00001C
H
RDR0
Port 0 pull-up resistor setting register
R/W
R/W
Port 0
00000000
B
00001D
H
RDR1
Port 1 pull-up resistor setting register
R/W
R/W
Port 1
00000000
B
00001E
H
to 1F
H
Prohibited area