- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377918 > MB90F462PFM (FUJITSU LTD) Octal Transparent D-type Latches With 3-State Outputs 20-CFP -55 to 125 PDF資料下載
參數(shù)資料
| 型號： | MB90F462PFM |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Octal Transparent D-type Latches With 3-State Outputs 20-CFP -55 to 125 |
| 中文描述： | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 59/85頁 |
| 文件大?。?/td> | 827K |
| 代理商： | MB90F462PFM |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁當前第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁
MB90460 Series
59
14. ROM Correction Function
In the case that the address of the instruction after the one that a program is currently processing matches the
address configured in the detection address configuration register, the program forces the next instruction to be
processed into an INT9 instruction, and branches to the interrupt process program. Since processing can be
conducted using INT9 interrupts, programs can be repaired using batch processing.
Overview of the Rom correction Function
The address of the instruction after the one that a program is currently processing is always stored in an
address latch via the internal data bus. Address match detection constantly compares the address stored in
the address latch with the one configured in the detection address configuration register. If the two compared
addresses match, the CPU forcibly changes this instruction into an INT9 instruction, and executes an interrupt
processing program.
There are two detection address configuration registers : PADR0 and PADR1. Each register provides an
interrupt enable bit. This allows you to individually configure each register to enable/prohibit the generation of
interrupts when the address stored in the address latch matches the one configured in the detection address
configuration register.
Block Diagram
Address latch
Stores value of address output to internal data bus.
Address detection control register (PACSR)
Set this register to enable/prohibit interrupt output when an address match is detected.
Detection address configuration register (PADR0, PADR1)
Configure an address with which to compare the address latch value.
PACSR
PADR0 (24 bit)
PADR1 (24 bit)
Address latch
Detection address configuration register 0
Detection address configuration register 1
C
INT9 instruction
(INT9 interrupt generation)
Re-
served
Re-
served
Re-
served
AD0E
Re-
served
AD1E
Re-
served
Re-
served
I
Address detection control register (PACSR)
Reseved : Make sure this is always set to “01”
相關PDF資料 |
PDF描述 |
|---|---|
| MB90470 | 16-Bit Proprietary Microcontroller |
| MB90470B | 16-Bit Proprietary Microcontroller |
| MB90473 | 16-Bit Proprietary Microcontroller |
| MB90473PF | 16-Bit Proprietary Microcontroller |
| MB90473PFV | 16-Bit Proprietary Microcontroller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MB90F474HPF-GE1 | 制造商:FUJITSU 功能描述:IC 16BIT MCU I2C SMD QFP100 |
| MB90F474HPFR-GE1 | 制造商:FUJITSU 功能描述: |
| MB90F474HPMC-GE1 | 制造商:FUJITSU 功能描述: |
| MB90F474LPFR-GE1 | 制造商:FUJITSU 功能描述: |
| MB90F474LPMCR-GE1 | 制造商:FUJITSU 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。