參數(shù)資料
型號: MB90F897
廠商: Fujitsu Limited
英文描述: 10-Bit Buffers/Drivers With 3-State Outputs 24-CFP -55 to 125
中文描述: 16位微控制器專有
文件頁數(shù): 24/78頁
文件大小: 746K
代理商: MB90F897
MB90895 Series
24
I
PERIPHERAL RESOURCES
1.
I/O Ports
The I/O ports are used as general-purpose input/output ports (parallel I/O ports). The MB90895 series model
is provided with 5 ports (34 inputs). The ports function as input/output pins for peripheral functions also.
I/O port functions
An I/O port, using port data resister (PDR), outputs the output data to I/O pin and input a signal input to I/O port.
The port direction register (DDR) specifies direction of input/output of I/O pins on a bit-by-bit basis.
The following summarizes functions of the ports and sharing peripheral functions :
Port 1 : General-purpose input/output port, used also for PPG timer output and input capture inputs.
Port 2 : General-purpose input/output port, used also for reload timer input/output and external interrupt input.
Port 3 : General-purpose input/output port, used also for A/D converter activation trigger pin.
Port 4 : General-purpose input/output port, used also for UART input/output and CAN controller send/receive
pin.
Port 5 : General-purpose input/output port, used also analog input pin.
Port 1 pins block diagram (single-chip mode)
Port 1 registers (single-chip mode)
Port 1 registers include port 1 data register (PDR1) and port 1 direction register (DDR1).
The bits configuring the register correspond to port 1 pins on a one-to-one basis.
Relation between port 1 registers and pins
Port name
Bits of register and corresponding pins
Port 1
PDR1, DDR1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pins
P17
P16
P15
P14
P13
P12
P11
P10
Pch
Nch
Peripheral
function input
Peripheral
function output
Port data register (PDR)
PDR read
Output latch
PDR write
Peripheral function
output permission
Pin
Port direction register (DDR)
Direction
latch
DDR write
DDR read
Standby control (SPL=1)
Standby control : Control among Stop mode (SPL=1), Time-base timer mode (SPL=1), and clock mode
(SPL=1).
I
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