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參數(shù)資料
| 型號： | MB90M407APF |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-Bit Original Microcontroller |
| 中文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 36/64頁 |
| 文件大?。?/td> | 310K |
| 代理商： | MB90M407APF |
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MB90M405 Series
36
8.
DTP/External Interrupt Circuit
The DTP (Data Transfer Peripheral) /external interrupt circuit detects interrupt requests input from the external
interrupt input pin, and outputs interrupt requests.
DTP/External Interrupt Function
The DTP/external interrupt circuit outputs interrupt requests upon detection of an edge input from the external
interrupt input pin, or a level signal. Interrupt requests are accepted by the CPU, and if extended intelligent I/O
service (EI
2
OS) is enabled, the CPU conducts automated data transfer (DTP function) via EI
2
OS, then branches
into an interrupt processing routine. If EI
2
OS is disabled, the CPU branches into an interrupt processing routine,
without starting automated data transfer (DTP function) via EI
2
OS.
ICR : Interrupt Control Register
DTP/External Interrupt Circuit Interrupts and EI
2
OS
External Interrupt Function
DTP Function
Input pins
4 channels (P80/INT0, P81/INT1, PB6/INT2, PB7/INT3)
Interrupt conditions
The level or edge to detect can be set independently for each pin in the detection level
setup register (ELVR)
“L” level/“H” level input
Rising edge/falling edge input
Interrupt number
#11 (0B
H
), #13 (0D
H
) , #16(10
H
)
Interrupt control
Enable/disable interrupt request output in the DTP/external interrupt enable register
(ENIR)
Interrupt flag
The DTP/interrupt factor register (EIRR) stores interrupt conditions.
Processing selection
Set EI
2
OS to disabled
(ICR : ISE
=
“0”)
Set EI
2
OS to enabled
(ICR : ISE
=
“1”)
Branch to interrupt processing routine after
automatic data transfer by EI
2
OS completes.
Operation
Branch to interrupt processing routine
Channel
Interrupt No.
Interrupt Control Register
Vector Table Address
EI
2
OS
Register Name
Address
Lower
Upper
Bank
INT0
#11 (0B
H
)
ICR00
0000B0
H
FFFFD0
H
FFFFD1
H
FFFFD2
H
INT1
#13 (0D
H
)
ICR01
0000B1
H
FFFFC8
H
FFFFC9
H
FFFFCA
H
INT2
#16 (10
H
)
ICR02
0000B2
H
FFFFBC
H
FFFFBD
H
FFFFBE
H
INT3
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