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參數(shù)資料
| 型號： | MB91107PFV-G |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP120 |
| 封裝： | PLASTIC, LQFP-120 |
| 文件頁數(shù)： | 79/111頁 |
| 文件大?。?/td> | 1337K |
| 代理商： | MB91107PFV-G |
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MB91107
7
(Continued)
Pin no.
Pin name
Circuit
type
Function
72
NMI
H
NMI (non-maskable interrupt pin) input (“L” active).
42
SC2/PE0
F
(SC2) Clock I/O pin for UART2.
Clock output is available when clock output of UART2 is enabled.
(PE0) General purpose I/O port.
This function is available when UART2 clock output is disabled.
43
DREQ0/PE1
F
(DREQ0) External transfer request input pins for DMA. This pin is used
for input when external trigger is selected to cause DMAC operation, and
it is necessary to disable output for other functions from this pin unless
such output is made intentionally.
(PE1) General purpose I/O port.
44
DACK0/PE2
F
(DACK0) External transfer request acknowledge output pin for DMAC
(ch. 0). This function is available when transfer request output for DMAC
is enabled.
(PE2) General purpose I/O port.
This function is available when transfer request acknowledge output for
DMAC or DACK0 output is disabled.
45
EOP0/PE3
F
(EOP0) Can be configured as DMAC EOP OUTPUT (ch.0) when DMAC
EOP output is enable.
(PE3) General purpose I/O port.
46
DREQ1/PE4
F
(DREQ1) External transfer request input pins for DMA. This pin is used
for input when external trigger is selected to cause DMAC operation, and
it is necessary to disable output for other functions from this pin unless
such output is made intentionally.
(PE4) General purpose I/O port.
47
DACK1/PE5
F
(DACK1) External transfer request acknowledge output pin for DMAC
(ch. 1). This function is available when transfer request output for DMAC
is enabled.
(PE5) General purpose I/O port.
This function is available when transfer request acknowledge output for
DMAC or DACK1 output is disabled.
48
EOP1/PE6
F
(EOP1) Can be configured as DMAC EOP OUTPUT (ch.1) when DMAC
EOP output is enable.
(PE6) General purpose I/O port.
49
DREQ2/PE7
F
(DREQ2) External transfer request input pins for DMA.
This pin is used for input when external trigger is selected to cause
DMAC operation, and it is necessary to disable output for other functions
from this pin unless such output is made intentionally.
(PE7) General purpose I/O port.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB91108PFV | 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP120 |
| MB91107PFV | 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP120 |
| MB91110PMT2 | 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP144 |
| MB91110PMT2 | 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP144 |
| MB91121PFV | 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP120 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB91108 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit RISC Microcontroller |
| MB91108PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit RISC Microcontroller CMOS |
| MB91110 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-Bit RISC Microcontroller |
| MB911110PMT2 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-Bit RISC Microcontroller |
| MB91121 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit RISC Microcontroller |
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