參數(shù)資料
型號(hào)： MB91306RPFV
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-Bit Microcontroller
中文描述： 32-BIT, 66 MHz, RISC MICROCONTROLLER, PQFP120
封裝： LEAD FREE, PLASTIC, LQFP-120
文件頁(yè)數(shù)： 20/96頁(yè)
文件大?。?/td> 963K
代理商： MB91306RPFV
MB91307 Series
20
RMW instructions using R15
If one of the instructions listed below is executed, the value of SSP or USP* is not used as the value of R15 and,
as a result, an incorrect value is written to memory. Therefore, the compiler does not generate the following
instructions:
AND
OR
EOR
XCHB
R15,@Rj
R15,@Rj
R15,@Rj
@Rj,R15
ANDH
ORH
EORH
R15,@Rj
R15,@Rj
R15,@Rj
ANDB
ORB
EORB
R15,@Rj
R15,@Rj
R15,@Rj
* : R15 is an insubstantial register. If R15 is accessed by a program, SSP or USP is accessed according to the
state of the S flag of the PS register.
Avoid this notes as follows:
When programming any of the above 10 instructions by an assembler, specify a general-purpose register in
place of R15.
Executing instructions on RAM
If instruction codes are placed in RAM, they should not be placed in the last 8 address bytes 0005 FFF8
H
to
0005 FFFF
H
. (Instruction code prohibited area)
Notes on the PS register
Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt
handler to break or the PS flag to update its display setting when the debugger is being used. As the microcon-
troller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs oper-
ations before and after the EIT as specified in either case.
The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS
instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data
event or emulator menu:
(1) D0 and D1 flags are updated earlier.
(2) The EIT handler (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are
updated to the same values as those in (1) above.
The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are executed
to enable interruptions when a user interrupt or NMI trigger event has occurred.
(1) The PS register is updated earlier.
(2) The EIT handler (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the
same value as that in (1) above.
Notes on I-bus Memory
Do not access data in the instruction cache control register or the instruction cache RAM immediately before
the RETI instruction.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB91307 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-Bit Microcontroller
MB91307B 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-Bit Microcontroller
MB91307BPFV 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-Bit Microcontroller
MB91307RPFV 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-Bit Microcontroller
MB91310 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:Proprietary 32-bit Microcontroller
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