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MB91307 Series
3
(Continued)
UART
Full duplex double buffer
3-channel
Parity/no parity selection
Asynchronous (start-stop synchronized), CLK-synchronized communications selection
Built-in exclusive baud rate timer
External clock can be used as transfer clock
Variety of error detection functions (parity, frame, overrun)
I
2
C* interface
Master/slave sending and receiving
Clock synchronization function
Transfer direction detection function
Bus error detection function
Operates in standard mode (Max 100 Kbps) or high speed mode (Max 400 Kbps)
Interrupt controller
Total of 9 external interrupts: 1 non-maskable interrupt pin (NMI) and 8 normal interrupt pins INT7-INT0
Interrupt from internal peripheral devices
Programmable priority settings (16 levels) enabled, except for non-maskable interrupt
Can be used for wake-up from stop mode
A/D converter
10-bit resolution, 4-channel
Sequential comparator type, conversion time approx. 5.4
μ
s
Conversion modes: single conversion mode, continuous conversion mode
Startup source: software / external trigger / timer output signal
Other interval timers
16-bit timer with 3 channels (U-timer)
Watchdog timer
I/O port
Maximum 69 ports
Other features
Built-in oscillator circuit for clock source, PLL multiplier selection enabled
INIT reset pin
Also included: watchdog timer reset, software reset
Power-saving modes: stop mode, sleep mode supported
Gear functions
Built-in time base timer
Packages: LQFP-120 (FPT-120P-M21) : MB91306R, MB91307R
: MB91V307R (Evaluation products)
: 0.25
μ
m : MB91V307R, 0.18
μ
m : MB91306R, MB91307R
: MB91V307R : 3.3 V
±
0.3 V (built-in regulator 3.3 V
→
2.5 V)
: MB91306R, MB91307R : 3.3 V
±
0.3 V, 1.8V
±
0.15 V dual power supplies
CMOS technology
Supply voltage
* : Purchase of Fujitsu I
2
C components conveys a license under the Philips I
2
C Patent rights to use, these components
in an I
2
C system provided that the system conforms to the I
2
C Standard Specification as defined by Philips.
Arbitration function
Slave address/general call address detection function
Start condition repeat generator and detection function
10-bit/7-bit slave address