- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄69022 > MB91F223SPFV-GSE1 RISC MICROCONTROLLER, PQFP144 PDF資料下載
參數(shù)資料
| 型號(hào)： | MB91F223SPFV-GSE1 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 18/46頁 |
| 文件大小： | 2487K |
| 代理商： | MB91F223SPFV-GSE1 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當(dāng)前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
USB DEVICE CONTROLLER
M66290AGP/FP
MITSUBISHI <DIGITAL ASSP>
31
Af ter "Data1" read end
"Data2" receiv e end
"Data3" receiv e start
"Data1" read start
"Data2" receiv e start
"Data1" receiv e end
"Data1" receiv e start
Bef ore "Data1" read end
"Data2" receiv e end
"Data1" read end
When data receiv e ended, the buff er
is set to Ready state (read enable)
and occurs INTR interrupt
Continuous receiv ing is av ailable
bef ore data read.
In OUT token receiv e to this
INTN interrupt and do NAK
handshake.
endpoint, M66290A occurs
It becomes receiv e enable
af ter read of data1 ended.
And occurs INTR interrupt
because the buff er is ready.
M66290A Occurs INTR interrupt
because the buff er is ready.
data1
data2
receiving data
Buff er1
Buff er2
USB side
CPU bus side
Buff er2
Buff er1
data receive
available
data receive completed
data read available
Buff er2
Buff er1
data1
data2
receiving data
data read available
data1
Buff er2
Buff er1
IN
receiving data
reading data
Buff er2
Buff er1
data receive completed
data receive impossible
reading data
OUT
data1
OUT
Buff er1
Buff er2
data receive enable
data read available
data2
Buff er1
Buff er2
data receive available
data read available
data2
Buff er1
Buff er2
data2
data3
receiving data
data read available
IN
data
: Data exists in buff er
(1) Receiv ing
Below are the receiv e status examples
of the endpoint which is set to double buff er.
Endpoint buffer status
Figure 7. Double buff er activ ities-1
Double buffer operations
The endpoint FIFO of EP1 to EP5 can be
set to double buffer constitution.
So a double of transfer data of its buffer size, which
is set, can be stored.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB91F267APMC | 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP64 |
| MB91F267NAPMC | 32-BIT, FLASH, 33 MHz, RISC MICROCONTROLLER, PQFP64 |
| MB91F361GAPFVS | 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP208 |
| MB91F361G | 32-BIT, MROM, 64 MHz, MICROCONTROLLER, PQFP208 |
| MB91F368GA | 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP120 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB91F233 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91F233APFF-GE1 | 制造商:FUJITSU 功能描述:IC 32BIT MCU 5V SMD LQFP120 |
| MB91F233L | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91F233LLGA-GE1 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91F233LPFF-GE1 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。