參數(shù)資料
型號: MB91F353APMT
元件分類: 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, PQFP120
封裝: 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PPITCH, LEAD FREE, PLASTIC, LQFP-120
文件頁數(shù): 103/140頁
文件大?。?/td> 3803K
代理商: MB91F353APMT
MB91350A Series
DS07-16503-5E
65
4.
8/16-bit Up/Down Counter
(1) Description
This block is the up/down counter/timer consisting of six event input pins, two 8-bit up/down counter, two 8-bit
reload/compare registers, and their control circuit.
The MB91F355A/F356B/F357B/355A/354A/V350A contains 2 channels of 8-bit up/down counter in this block.
The MB91F353A/353A/352A/351A contains 1 channel of 8-bit up/down counter in this block. It is not possible
to use in 16-bit mode.
This module has the following features.
8-bit count register enabling counting from (0)d to (255)d
(enabling counting from (0)d to (65535)d in 16 bits
× 1 operation mode)
Four different count modes available with selectable count clocks
In timer mode, the ability to select the count clock input to use from among two internal clock circuits
In up/down count mode, the ability to select the edge detection of the external pin input signals
The phase difference count mode is suitable for counting encoders such as motor encoders, and facilitates to
count the angle of revolution and number of revolutions to a high precision by inputting the A phase, B phase,
and Z phase outputs from the encoder
ZIN pin has two selectable functions (valid in all modes)
Compare and reload functions that can be used separately or in combination. When both functions are used
in combination, up/down counting can be performed at an arbitrary width.
Count direction flag used to identify the preceding count direction
Capable of independently controlling the generation of interrupts for compare match, reload (underflow),
overflow, or on count direction change
Count mode
Timer mode
Up/down count mode
Phase difference count mode (2 Multiplication)
Phase difference count mode (4 Multiplication)
Count clock
(When operating at
25 MHz)
80 ns (12.5 MHz : Frequency division by 2)
320 ns (3.125 MHz : Frequency division by 8)
Detection edge
Falling edge detection
Rising edge detection
Detection at rising edge, falling edge, or both edges
Edge detection disabled
ZIN pin
Counter clear function
Gate function
Compare/reload
function
Compare function (output interrupt request on compare match)
Compare function (output interrupt request and clear counter on compare
match)
Reload function (output interrupt request and reload on underflow)
Compare/reload function
(output interrupt request and clear counter on compare match; output interrupt
request and reload on underflow)
Compare/reload disabled
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