參數(shù)資料
型號: MB91F353APMT
元件分類: 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, PQFP120
封裝: 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PPITCH, LEAD FREE, PLASTIC, LQFP-120
文件頁數(shù): 6/140頁
文件大小: 3803K
代理商: MB91F353APMT
MB91350A Series
DS07-16503-5E
103
(4) Normal Bus Access Read/Write Operation
MB91F353A/353A/352A/351A
(VCC
= 3.0 V to 3.6 V, VSS = DAVS = AVSS = 0 V, Ta = 40 °C to + 85 °C)
*1 : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (tCYC
× the number of
cycles added for the delay) to this rating.
*2 : This value is the rating when the gear ratio is set to
× 1. For the ratings when the gear ratio is set to between 1/2 to
1/16, substitute 1/2 to 1/16 for n in the following equation.
Calculation expression : 3/(2n)
× tCYC 15
*3 : AWRxL : Area Wait Register
*4 : The MB91F353A/353A/352A/351A does not have A23 to A21.
Note : tCYC represents the cycle time. Refer to “(2) Clock Output Timing”.
Parameter
Symbol
Pin name
Conditions
Value
Unit
Remarks
Min
Max
CS0 to CS3 setup
tCSLCH
SYSCLK,
CS0 to CS3
AWRxL : W02
= 03
ns
*3
tCSDLCH
AWR0L : W02
= 1
3
CS0 to CS3 hold
tCHCSH
3
tCYC
/ 2 + 6
Address setup
tASCH
SYSCLK,
A20 to A00*4
tASWL
WR0, WR1,
A20 to A00*4
tASRL
RD,
A20 to A00*4
Address hold
tCHAX
SYSCLK,
A20 to A00*4
tCYC
/ 2 + 6
tWHAX
WR0, WR1,
A20 to A00*4
tRHAX
RD,
A20 to A00*4
Valid address
Valid data input time
tAVDV
A20 to A00*4,
D31 to D16
3
/ 2 × tCYC 15
*1
*2
WR0, WR1 delay time
tCHWL
SYSCLK,
WR0, WR1
6
WR0, WR1 delay time
tCHWH
WR0, WR1 minimum
pulse width
tWLWH
WR0, WR1
tCYC
5
Data setup
→ WRx ↑
tDSWH
WR0, WR1,
D31 to D16
tCYC
WRx
↑ → Data hold time
tWHDX
3
RD delay time
tCHRL
SYSCLK,
RD
6
RD delay time
tCHRH
RD
↓ → Valid data input
time
tRLDV
RD,
D31 to D16
tCYC
10
*1
Data setup
→ RD ↑ Time
tDSRH
10
RD
↑ → Data hold time
tRHDX
0
RD minimum pulse width
tRLRH
RD
tCYC
5
AS setup
tASLCH
SYSCLK,
AS
3
AS hold
tCHASH
tCYC
/ 2 + 6
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