參數資料
型號: MB91V301A
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 68 MHz, RISC MICROCONTROLLER, CPGA179
封裝: CERAMIC, PGA-179
文件頁數: 71/140頁
文件大?。?/td> 2841K
代理商: MB91V301A
MB91301 Series
36
DS07-16502-4E
■ MODE SETTINGS
In the FR family, the mode is set by the mode pins (MD2, MD1, and MD0) and mode register (MODR).
1.
Mode Pins
The MD2, MD1, and MD0 pins specify how the mode vector fetch is performed.
Values other than those listed in the table are prohibited.
* : Single chip mode is able to set only MB91302A.
2.
Mode Register (MODR)
Details of mode register (MODR)
The data written to the mode register by the mode vector fetch operation (see “3.11.3 reset sequences”) is
called the mode data.
After the data is set to the mode register (MODR), the device operates with the operating mode specified by
this data. The mode register is set by all types of reset. The register cannot be written to by user programs.
<Details of mode register (MODR) >
<Details of mode data>
Bit31 to bit24 are all reserved bits.
Be sure to set this bit to “00000”.
Operation is not guaranteed when any value other than “00000” is set.
Mode Pins
Mode name
Reset vector access
area
Remarks
MD2
MD1
MD0
0
Internal ROM vector mode
Internal
Single-chip mode*
0
1
External ROM vector mode
External
The bus width is specified by the
mode register.
bit
Address
Initial Value
XXXXXXXXB
23
22
21
20
19
18
17
16
ROMA
WTH1
WTH0
WW
W
Operation mode setting bits
bit
Address
Initial Value
XXXXXXXXB
31
30
29
28
27
26
25
24
ROMA
WTH1
WTH0
WW
W
Operation mode setting bits
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