參數(shù)資料
型號: MB91V301A
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 68 MHz, RISC MICROCONTROLLER, CPGA179
封裝: CERAMIC, PGA-179
文件頁數(shù): 91/140頁
文件大?。?/td> 2841K
代理商: MB91V301A
MB91301 Series
54
DS07-16502-4E
Control Registers
Cache Size Register (ISIZE)
Instruction Cache Control Register (ICHCR)
The instruction cache (I-cache) control register (ICHCR) controls the operations of the instruction cache.
Writing a value to the ICHCR has no effect on the caching of any instruction fetched within three cycles that follow.
bit
Initial value
Address : 00000307H
- - - - - - 10B
76
5
4
3
2
1
0
R/W
SIZE1
R/W
SIZE0
bit
Initial value
Address : 000003E7H
0 - 000000B
76
5
4
3
2
1
0
R/W
RAM
GBLK
ALFL
EOLK
ELKR
FLSH
R/W
ENAB
Address
00010000H
00010200H
00010400H
00010600H
00010800H
00010FFFH
TAG RAM
00010000H
00010004H
00010008H
0001000CH
00010010H
00010014H
00014000H
00014200H
00014400H
00014600H
00014800H
00014FFFH
00018000H
00018200H
00018400H
00018600H
00018800H
00018FFFH
0001C000H
0001C200H
0001C400H
0001C600H
0001C800H
0001CFFFH
Cache RAM
00018000H
00018004H
00018008H
0001800CH
00018010H
00018014H
Cache off
RAM off
Cache off
RAM on
TAG1
TAG2
IRAM1
IRAM2
<TAG1>
<TAG2>
<IRAM1>
<IRAM2>
IRAM1
IRAM2
IRAM1
IRAM2
<IRAM1>
<IRAM2>
IRAM1
IRAM2
<IRAM1>
<IRAM2>
TAG1
TAG2
$RAM1
$RAM2
<TAG1>
<TAG2>
<$RAM1>
<$RAM2>
TAG1
TAG2
$RAM1
$RAM2
<TAG1>
<TAG2>
<TAG1>
<TAG2>
<$RAM1>
<$RAM2>
IRAM1
IRAM2
TAG1
TAG2
$RAM1
$RAM2
<TAG1>
<TAG2>
<TAG1>
<TAG2>
<TAG1>
<TAG2>
<TAG1>
<TAG2>
<$RAM1>
<$RAM2>
Cache 4 K
RAM off
Cache 4 K
RAM on
Cache 2 K
RAM off
Cache 2 K
RAM on
Cache 1 K
RAM off
Cache
RAM on
TAG1
TAG RAM (way1)
TAG2
TAG RAM (way2)
<> Mirror area
RAM on/off
RAM bit = I/O
$RAM1
Cache RAM (way1) IRAM1 I-bus RAM (way1)
$RAM2
Cache RAM (way2) IRAM1 I-bus RAM (way2)
←Entry at address 00x
←Mirror of 00x
←Entry at address 00x
←Mirror of 00x
Instruction at address 000 (SBV0)
Instruction at address 004 (SBV1)
Instruction at address 008 (SBV2)
Instruction at address 00C (SBV3)
Instruction at address 010 (SBV0)
Instruction at address 014 (SBV1)
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