- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄69023 > MB91V301A 32-BIT, 68 MHz, RISC MICROCONTROLLER, CPGA179 PDF資料下載
參數(shù)資料
| 型號(hào)： | MB91V301A |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 68 MHz, RISC MICROCONTROLLER, CPGA179 |
| 封裝： | CERAMIC, PGA-179 |
| 文件頁(yè)數(shù)： | 90/140頁(yè) |
| 文件大?。?/td> | 2841K |
| 代理商： | MB91V301A |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)當(dāng)前第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)
MB91301 Series
DS07-16502-4E
53
Instruction Cache Tags
[bit31 to bit9] Address tag
The address tag stores the upper 23 bits of the memory address of the instruction cached in the corresponding
block.
For example, memory address IA of the instruction data stored in sub-block k in block i is obtained from the
following equation:
IA
= address tag × 29 + i × 24 + k × 22
The address tag is used to check for a match with the instruction address requested for access by the CPU.
The CPU and cache behave as follows depending on the result of the tag check:
When the requested instruction data exists in the cache (hit), the cache transfers the data to the CPU within
the cycle.
When the requested instruction data does not exist in the cache (miss), the CPU and cache obtain the data
loaded by external access at the same time.
[bit7 to bit4] SBV3 to SBV0 : Sub-block validation
When SBVn contains "1", the corresponding sub-block holds the current instruction data at the address located
by the tag. Each sub-block usually holds two instructions (excluding immediate-value transfer instructions).
[bit3] TAGV : Tag validation bit
This bit indicates whether the address tag value is valid. When the bit contains "0", the corresponding block is
invalid regardless of the settings of the sub-block validation bits. (The bit is set to "0" when the cache is flushed.)
[bit1] LRU (only in way 1)
This bit exists only in the instruction cache tag in way 1. The bit indicates way 1 or 2 as the way containing the
last entry accessed in the selected set. When set to "1", the LRU bit indicates that the entry of the set in way 1
is the last entry accessed. When set to "0", it indicates that the one in way 2 is the last entry accessed.
[bit0] ETLK : Entry lock
This bit is used to lock all the entries in the block corresponding to the tag in the cache. When the ETLK bit is
set to "1", the entries are locked and are not updated when a cache miss occurs. Note, however, that invalid
sub-blocks are updated. If a cache miss occurs with both of ways 1 and 2 in the entry lock states, access to
external memory takes place after losing one cycle used for evaluating the cache miss.
76
5
4
3
2
10
SBV2
SBV3
SBV1
SBV0
TAGV
LRU
ETLK
31
9
8
76
5
4
3
2
10
SBV2
SBV3
SBV1
SBV0
TAGV
ETLK
31
9
8
Address tag
Way 1
Way 2
Address tag
Vacancy
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB91302APFF-G-XXX-BNDE1 | 32-BIT, MROM, 68 MHz, RISC MICROCONTROLLER, PQFP144 |
| MB91302APFF-G-020-BNDE1 | 32-BIT, MROM, 68 MHz, RISC MICROCONTROLLER, PQFP144 |
| MB91302APFF-G-001-BNDE1 | 32-BIT, MROM, 68 MHz, RISC MICROCONTROLLER, PQFP144 |
| MB92411-33CR | 4 CHANNEL(S), 33 MHz, DMA CONTROLLER, CPGA179 |
| MB95108AHPFM | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB91V301A-RDK01 | 制造商:FUJI 制造商全稱:Fuji Electric 功能描述:32-Bit Proprietary Microcontroller |
| MB91V307RCR | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-Bit Microcontroller |
| MB91V350A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-Bit Proprietary Microcontroller |
| MB91V650 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontrollers |
| MB-920 | 制造商:Maxxtro 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。