參數(shù)資料
型號: MB95F396KPMC-G-SNE2
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, 1.70 MM HEIGHT, PLASTIC, LQFP-48
文件頁數(shù): 10/60頁
文件大?。?/td> 3064K
代理商: MB95F396KPMC-G-SNE2
MB95390H Series
18
DS07–12632–1E
■ BLOCK DIAGRAM
Reset with LVD
Dual operation Flash with
security function
(60 Kbyte)
F2MC-8FX CPU
RAM (496/1008/2032 bytes)
Oscillator
circuit
CR
oscillator
Clock control
On-chip debug
Wild register
External interrupt
Interrupt controller
LIN-UART
8/16-bit composite timer ch. 0
8/10-bit A/D converter
16-bit reload timer
MPG
16-bit PPG timer
8/16-bit PPG ch. 1
8/16-bit composite timer ch. 1
Waveform sequencer
UART/SIO
I2C
8/16-bit PPG ch. 0
8/16-bit PPG ch. 2
Port
PF2*1/RST*2
PF1/X1*2
PF0/X0*2
PG2/X1A*2
PG1/X0A*2
(P04)
(P05)
P00/INT00 to P07/INT07
C
P45/SCK
P46/SOT
P47/SIN
P75/UCK0
P76/UO0
P77/UI0
(P62/PPG00*3), P13/PPG00
(P63/PPG01*3), P14/PPG01
(P66/PPG20*3), P15/PPG20
(P67/PPG21*3), P16/PPG21
P72/SCL*1
P73/SDA*1
P12/DBG*1
P70/TO00
P71/TO01
P74/EC0
(P00/AN00 to P07/AN07)
P40/AN08 to P43/AN11
(P62/TO10)
(P63/TO11)
(P64/EC1)
(P61/TI1)
P44/TO1
P62/OPT0 to P67/OPT5*3
P17/SNI0, PG1/SNI1, PG2/SNI2
P60/DTTI
P61/TI1
(P67/TRG1)
(P66/PPG1)
P10/PPG10, (P64/PPG10*3)
P11/PPG11, (P65/PPG11*3)
Vcc
Vss
*1:
*2:
*3:
PF2, P12, P72 and P73 are N-ch open drain pins.
Software option
P62 to P67 are high-current pins.
Inter
n
a
l
bu
s
Note: Pins in parentheses indicate that functions of those pins are shared among different resources.
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