參數(shù)資料
型號: MB95F396KPMC-G-SNE2
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, 1.70 MM HEIGHT, PLASTIC, LQFP-48
文件頁數(shù): 37/60頁
文件大?。?/td> 3064K
代理商: MB95F396KPMC-G-SNE2
MB95390H Series
42
DS07–12632–1E
Sampling is executed at the falling edge of the sampling clock*1, and serial clock delay is disabled*2.
(ESCR register: SCES bit = 1, ECCR register: SCDE bit = 0)
(VCC = 5.0 V
±10%, VSS = 0.0 V, TA = 40°C to +85°C)
*1: There is a function used to choose whether the sampling of reception data is performed at a rising edge or
a falling edge of the serial clock.
*2: The serial clock delay function is a function used to delay the output signal of the serial clock for half the clock.
*3: See “(2) Source Clock/Machine Clock” for tMCLK.
Parameter
Symbol Pin name
Condition
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK
Internal clock
operation output pin:
CL = 80 pF
+ 1 TTL
5 tMCLK*3
—ns
SCK
↑ → SOT delay time
tSHOVI
SCK, SOT
95
+95
ns
Valid SIN
→ SCK ↓
tIVSLI
SCK, SIN
tMCLK*3
+ 190
ns
SCK
↓ → valid SIN hold time
tSLIXI
SCK, SIN
0
ns
Serial clock “H” pulse width
tSHSL
SCK
External clock
operation output pin:
CL = 80 pF
+ 1 TTL
3 tMCLK*3
tR
—ns
Serial clock “L” pulse width
tSLSH
SCK
tMCLK*3
+ 95
ns
SCK
↑ → SOT delay time
tSHOVE
SCK, SOT
2 tMCLK*3
+ 95 ns
Valid SIN
→ SCK ↓
tIVSLE
SCK, SIN
190
ns
SCK
↓ → valid SIN hold time
tSLIXE
SCK, SIN
tMCLK*3
+ 95
ns
SCK fall time
tF
SCK
10
ns
SCK rise time
tR
SCK
10
ns
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