參數(shù)資料
型號: MB95F396KPMC-G-SNE2
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 16.25 MHz, MICROCONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, 1.70 MM HEIGHT, PLASTIC, LQFP-48
文件頁數(shù): 12/60頁
文件大?。?/td> 3064K
代理商: MB95F396KPMC-G-SNE2
MB95390H Series
2
DS07–12632–1E
(Continued)
I2C
× 1 channel
Built-in wake-up function
Multi-pulse generator (MPG) (for DC motor control)
× 1 channel
16-bit reload timer
× 1 channel
16-bit PPG timer
× 1 channel
Waveform sequencer (including a 16-bit timer equipped with a buffer and a compare clear function)
LIN-UART
Full duplex double buffer
Capable of clock-synchronous serial data transfer and clock-asynchronous serial data transfer
External interrupt
× 8 channels
Interrupt by edge detection (rising edge, falling edge, and both edges can be selected)
Can be used to wake up the device from different low power consumption (standby) modes
8/10-bit A/D converter
× 12 channels
8-bit and 10-bit resolution can be chosen.
Low power consumption (standby) modes
Stop mode
Sleep mode
Watch mode
Time-base timer mode
I/O port
MB95F394H/F396H/F398H (maximum no. of I/O ports: 44)
General-purpose I/O ports (N-ch open drain)
: 3
General-purpose I/O ports (CMOS I/O)
: 41
MB95F394K/F396K/F398K (maximum no. of I/O ports: 45)
General-purpose I/O ports (N-ch open drain)
: 4
General-purpose I/O ports (CMOS I/O)
: 41
On-chip debug
1-wire serial control
Serial writing supported (asynchronous mode)
Hardware/software watchdog timer
Built-in hardware watchdog timer
Built-in software watchdog timer
Low-voltage detection reset circuit
Built-in low-voltage detector
Clock supervisor counter
Built-in clock supervisor counter function
Programmable port input voltage level
CMOS input level / hysteresis input level
Dual operation Flash memory
The erase/write operation and the read operation can be executed in different banks (upper bank/lower
bank) simultaneously.
Flash memory security function
Protects the content of the Flash memory
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