參數(shù)資料
型號: MB96F395YSBPMC-GSE2
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 56 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 71/96頁
文件大?。?/td> 2534K
代理商: MB96F395YSBPMC-GSE2
PRELIMINARY
MB96390 Series
FME-MB96390 rev 3
73
I2C Timing
*1 : For use at over 100 kHz, set the peripheral clock 1 to at least 6 MHz.
*2 : Cb = capacitance of one bus line in pF.
*3 : tCLKP1 is the cycle time of the periperal clock CLKP1.
VOH = 0.7 * VCC
VOL = 0.3 * VCC
CMOS Hysteresis 0.7/0.3 input selected
(TA = -40C to 125C, VCC = AVCC = 3.0V to 5.5V, VSS = AVSS = 0V)
Parameter
Symbol
Standard-mode
Fast-mode*1
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
0
100
0
400
kHz
Hold time (repeated) START condition
SDA
↓→SCL↓
tHDSTA
4.0
0.6
s
“L” width of the SCL clock
tLOW
4.7
1.3
s
“H” width of the SCL clock
tHIGH
4.0
0.6
s
Set-up time for a repeated START condition
SCL
↑→SDA↓
tSUSTA
4.7
0.6
s
Data hold time
SCL
↓→SDA↓↑
tHDDAT
0
3.45
0
0.9
s
Data set-up time
SDA
↓↑→SCL↑
tSUDAT
250
100
ns
Set-up time for STOP condition
SCL
↑→SDA↑
tSUSTO
4.0
0.6
s
Bus free time between a STOP and START
condition
tBUS
4.7
1.3
s
Output fall time from 0.7*Vcc to 0.3*Vcc with
a bus capacitance from 10 pF to 400 pF
tof
20 + 0.1*Cb *2
250
20 + 0.1*Cb *2
250
ns
Capacitive load for each bus line
Cb
400
400
pF
Pulse width of spikes which will be sup-
pressed by input noise filter
tSP
n/a
0
1*tCLKP1*3
ns
SDA
SCL
tLOW
tSUDAT
tHDSTA
tBUS
tHDSTA
tHDDAT
tHIGH
tSUSTA
tSUSTO
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