參數(shù)資料
型號: MBM29DL162BD-70PFTN
廠商: FUJITSU LTD
元件分類: PROM
英文描述: 1M X 16 FLASH 3V PROM, 70 ns, PDSO48
封裝: PLASTIC, TSOP1-48
文件頁數(shù): 35/74頁
文件大小: 1170K
代理商: MBM29DL162BD-70PFTN
MBM29DL16XTD/BD-70/90
40
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than VLKO. If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled.
Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level
is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent
unintentional writes when VCC is above VLKO.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
Sector Group Protection
Device user is able to protect each sector group individually to store and protect data. Protection circuit voids
both program and erase commands that are addressed to protected sectors.
Any commands to program or erase addressed to protected sector are ignored (see “s FUNCTIONAL
DESCRIPTION Sector Group Protection”)
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