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參數(shù)資料
| 型號： | MBM29DL640E12PBT |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | 64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| 中文描述： | 4M X 16 FLASH 3V PROM, 120 ns, PBGA63 |
| 封裝： | PLASTIC, FBGA-63 |
| 文件頁數(shù)： | 36/71頁 |
| 文件大?。?/td> | 913K |
| 代理商： | MBM29DL640E12PBT |
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MBM29DL640E
80/90/12
36
However, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ
5
is high (see the section on DQ
5
) . If it is, the system should then
determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ
5
went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase
operation. If it is still toggling, the device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ
5
has not
gone high. The system may continue to monitor the toggle bit and DQ
5
through successive read cycles, deter-
mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the
status of the operation. (Refer to Figure 25.)
Table 13
Toggle Bit Status
Note : Successive reads from the erasing or erase-suspend sector will cause DQ
2
to toggle. Reading from the non-
erase suspend sector address will indicate logic “1” at the DQ
2
bit.
RY/BY
Ready/Busy
The device provides a RY/BY open-drain output pin as a way to indicate to the host system that Embedded
Algorithms are either in progress or have been completed. If output is low, the device is busy with either a program
or erase operation. If output is high, the device is ready to accept any read/write or erase operation. If the device
is placed in an Erase Suspend mode, RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during RESET pulse. Refer to Figures 13 and 14 for a detailed timing diagram. The RY/BY pin
is pulled high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to V
CC
.
Byte/Word Configuration
BYTE pin selects byte (8-bit) mode or word (16-bit) mode for the device. When this pin is driven high, the device
operates in word (16-bit) mode. Data is read and programmed at DQ
15
to DQ
0
. When this pin is driven low, the
device operates in byte (8-bit) mode. In this mode, the DQ
15
/A
-1
pin becomes the lowest address bit, and DQ
14
to DQ
8
bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands
are written at DQ
7
to DQ
0
and DQ
15
to DQ
8
bits are ignored. Refer to Figures 15, 16 and 17 for the timing diagram.
Data Protection
The device is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transitions. During power-up, the device automatically resets the internal
state machine in Read mode. Also, with its control register architecture, alteration of memory contents only
occurs after successful completion of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from V
CC
power-up
and power-down transitions or system noise.
Mode
DQ
7
DQ
6
DQ
2
Program
DQ
7
Toggle
1
Erase
0
Toggle
Toggle (Note)
Erase-Suspend Read
(Erase-Suspended Sector)
1
1
Toggle
Erase-Suspend Program
DQ
7
Toggle
1 (Note)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29DL640E12TN | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| MBM29DL640E12TR | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| MBM29DL640E80 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| MBM29DL640E80PBT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:64 M (8 M X 8/4 M X 16) BIT Dual Operation |
| MBM29DL640E80TN | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:64 M (8 M X 8/4 M X 16) BIT Dual Operation |
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