參數(shù)資料
型號(hào)： MBM29DL64DF
廠商： Fujitsu Limited
英文描述： FLASH MEMORY CMOS 64 M (8 M X 8/4 M X 16) BIT
中文描述： 閃存的CMOS 64米（8的MX 8 / 4的MX 16）位
文件頁(yè)數(shù)： 25/68頁(yè)
文件大?。?/td> 854K
代理商： MBM29DL64DF
MBM29DL64DF
-70
25
Output Disable
With the OE input at a logic high level (V
IH
) , output from the device is disabled. This causes the output pins to
be in a high impedance state.
Autoselect
Autoselect mode allows reading out of binary code and identifies its manufacturer and type.It is intended for use
by programming equipment for the purpose of automatically matching the device to be programmed with its
corresponding programming algorithm. This mode is functional over the entire temperature range of the device.
To activate this mode, the programming equipment must force V
ID
on address pin A
9
. Three identifier bytes may
then be sequenced from the device outputs by toggling addresses. All addresses can be either High or Low
except A
6
, A
3
, A
2
, A
1
, A
0
and (A
-1
) See User Bus Operations.
The manufacturer and device codes may also be read via the command register, for instances when the device
is erased or programmed in a system without access to high voltage on the A
9
pin. The command sequence is
illustrated in “Command Definitions”.
In the command Autoselect mode, the bank addresses BA; (A
21
, A
20
, A
19
) must point to a specific bank during
the third write bus cycle of the Autoselect command. Then the Autoselect data will be read from that bank while
array data can be read from the other bank.
In Word mode, a read cycle from address 00h returns the manufacturer’s code (Fujitsu
=
04h) . A read cycle at
address 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended
Device Codes is required. Therefore the system may continue reading out these Extended Device Codes at
addresses of 0Eh and 0Fh. Notice that the above applies to Word mode; the addresses and codes differ from
those of Byte mode (refer to “Sector Group Protection Verify Autoselect Codes Table” and “Extended Autoselect
Code Table” in
I
DEVICE BUS OPERATION.
In the case of applying V
ID
on A
9
, as both Bank 1 and Bank 2 enter Autoselect mode, simultanous operation
cannot be executed.
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as input to the internal state machine. The state machine output dictates the device function.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The com-
mand register is written by bringing WE to V
IL
, while CE is at V
IL
and OE is at V
IH
. Addresses are latched on the
falling edge of WE or CE, whichever starts later, while data is latched on the rising edge of WE or CE, whichever
starts first. Standard microprocessor write timings are used.
Refer to “
I
AC WRITE CHARACTERISTICS” and Erase/Programming Waveforms for specific timing parameters.
Sector Group Protection
The device features hardware sector group protection. This feature disables both program and erase operations
in any combination of forty eight sector groups of memory. See “Sector Group Address Table”. The user‘s side
can use sector group protection using programming equipment. The device is shipped with all sector groups
unprotected.
To activate it, the programming equipment must force V
ID
on address pin A
9
and control pin OE, CE
=
V
IL
and
A
6
=
A
3
=
A
2
=
A
0
=
V
IL
, A
1
=
V
IH
. The sector group addresses (A
21
, A
20
, A
19
, A
18
, A
17
, A
16
, A
15
, A
14
, A
13
and A
12
)
should be set to the sector to be protected. Sector Address Tables (Bank A to Bank D) define the sector address
for each of the one hundred forty-two (142) individual sectors, and Sector Group Address Table defines the
sector group address for each of the forty eight (48) individual group sectors. Programming of the protection
circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector
group addresses must be held constant during the WE pulse. See Sector Group Protection waveforms and
algorithms.
To verify programming of the protection circuitry, the programming equipment must force V
ID
on address pin A
9
with CE and OE at V
IL
and WE at V
IH
. Scanning the sector group addresses (A
21
, A
20
, A
19
, A
18
, A
17
, A
16
, A
15
, A
14
,
A
13
and A
12
) while (A
6
, A
3
, A
2
, A
1
, A
0
)
=
(0, 0, 0, 1, 0) produces a logica “1” code at device output DQ
0
for a
protected sector. Otherwise the device produces “0” for unprotected sectors. In this mode, the lower order
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