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參數(shù)資料
| 型號(hào)： | MBM29DL64DF |
| 廠商： | Fujitsu Limited |
| 英文描述： | FLASH MEMORY CMOS 64 M (8 M X 8/4 M X 16) BIT |
| 中文描述： | 閃存的CMOS 64米（8的MX 8 / 4的MX 16）位 |
| 文件頁數(shù)： | 30/68頁 |
| 文件大?。?/td> | 854K |
| 代理商： | MBM29DL64DF |
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MBM29DL64DF
-70
30
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program prior to erase. Upon executing the Embedded Erase Algorithm
command sequence, the device automatically programs and verifies the entire memory for an all-zero data
pattern prior to electrical erase (Preprogram function) . The system is not required to provide any controls or
timings during these operations.
The system can determine the erase operation status by using DQ
7
(Data Polling) , DQ
6
(Toggle Bit) or RY/BY.
The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence,
and terminates when the data on DQ
7
is “1” (see “Write Operation Status” section) , at which the device returns
to the read mode.
Chip Erase Time : Sector Erase Time
×
All sectors
+
Chip Program Time (Preprogramming)
“(2) Embedded Erase
TM
Algorithm” in
I
FLOW CHART illustrates the Embedded Erase
TM
Algorithm using typical
command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of CE or WE, whichever
starts later, while the command (Data
=
30h) is latched on the rising edge of CE or WE, whichever starts first.
After time-out of “t
TOW
” from the rising edge of the last sector erase command, the sector erase operation begins.
Multiple sectors are erased concurrently by writing the six bus cycle operations on Command Definitions. This
sequence is followed by writes of the Sector Erase command to addresses in other sectors desired to be
concurrently erased. The time between writes must be less than “t
TOW
”. Otherwise that command is not accepted
and erasure does not start. It is recommended that processor interrupts be disabled during this time to guarantee
such condition. The interrupts can reoccur after the last Sector Erase command is written. A time-out of “t
TOW
”
from the rising edge of last CE or WE, whichever starts first, initiates the execution of the Sector Erase command
(s) . If another falling edge of CE or WE, whichever starts first occurs within the “t
TOW
” time-out window, the timer
is reset (monitor DQ
3
to determine if the sector erase timer window is still open, see section DQ
3
, Sector Erase
Timer) . Resetting the device once execution begins may corrupt the data in the sector. In that case restart the
erase on those sectors and allow them to complete. Refer to “Write Operation Status” section for Sector Erase
Timer operation. Loading the sector erase buffer may be done in any sequence and with any number of sectors
(0 to 141) .
Sector erase does not require the user to program the device before erase. The device automatically programs
all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function) . When erasing
a sector, the rest remain unaffected. The system is not required to provide any controls or timings during these
operations.
The system can determine the status of the erase operation by using DQ
7
(Data Polling) , DQ
6
(Toggle Bit) or
RY/BY.
The sector erase begins after the “t
TOW
” time-out from the rising edge of CE or WE, whichever starts first, for the
last sector erase command pulse and terminates when the data on DQ
7
is “1” (see “Write Operation Status”
section) at which the device returns to the read mode. Data polling and Toggle Bit must be performed at an
address within any of the sectors being erased.
Multiple Sector Erase Time
=
[Sector Erase Time
+
Sector Program Time (Preprogramming) ]
×
Number of
Sector Erase
In case of multiple sector erase across bank boundaries, a read from the bank (read-while-erase) to which
sectors being erased belong cannot be performed.
“(2) Embedded Erase
TM
Algorithm” in
I
FLOW CHART illustrates the typical command strings and bus operations.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MBM29DL64DF-70 | FLASH MEMORY CMOS 64 M (8 M X 8/4 M X 16) BIT |
| MBM29DL64DF70PBT | FLASH MEMORY CMOS 64 M (8 M X 8/4 M X 16) BIT |
| MBM29DL64DF70TN | FLASH MEMORY CMOS 64 M (8 M X 8/4 M X 16) BIT |
| MBM29DL800TA | 8M (1M X 8/512K X 16) BIT |
| MBM29DL800BA-70 | LED Lamp; Bulb Size:T-1 3/4; LED Color:Red; Luminous Intensity:2000ucd; Viewing Angle:16 ; Forward Current:20mA; Forward Voltage:1.9V; Operating Temperature Range:-25 C to +85 C; Color:Red; Leaded Process Compatible:Yes RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29DL64DF-70 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:FLASH MEMORY CMOS 64 M (8 M X 8/4 M X 16) BIT |
| MBM29DL64DF70PBT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:FLASH MEMORY CMOS 64 M (8 M X 8/4 M X 16) BIT |
| MBM29DL64DF70TN | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:FLASH MEMORY CMOS 64 M (8 M X 8/4 M X 16) BIT |
| MBM29DL800BA | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8M (1M X 8/512K X 16) BIT |
| MBM29DL800BA-12 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8M (1M X 8/512K X 16) BIT |
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