- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377942 > MBM29F002TC-90 (Fujitsu Limited) 2M (256K X 8) BIT PDF資料下載
參數(shù)資料
| 型號： | MBM29F002TC-90 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 2M (256K X 8) BIT |
| 中文描述： | 200萬（256K × 8）位 |
| 文件頁數(shù)： | 20/46頁 |
| 文件大?。?/td> | 461K |
| 代理商： | MBM29F002TC-90 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁
20
MBM29F002TC
-55/-70/-90
/MBM29F002BC
-55/-70/-90
Data Protection
The MBM29F002TC/BC is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the device automatically
resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completions of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from V
CC
power-up
and power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than 3.2 V (typically 3.7 V). If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when V
CC
is above 3.2 V.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
or WE = V
IH
. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the device with WE = CE = V
IL
and OE = V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to the read mode on power-up.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MBM29F002B | 2M (256K ×8) Bit Flash Memory( 單5V 電源電壓256K ×8位閃速存儲器) |
| MBM29F002SB | 2M (256K ×8) Bit Flash Memory( 單5V 電源電壓256K ×8位閃速存儲器) |
| MBM29F002ST | 2M (256K ×8) Bit Flash Memory( 單5V 電源電壓256K ×8位閃速存儲器) |
| MBM29F002T | 2M (256K ×8) Bit Flash Memory( 單5V 電源電壓256K ×8位閃速存儲器) |
| MBM29F016-12 | CMOS 16M (2M x 8) Bit Flash Memory(CMOS 16M (2M x 8)位閃速存儲器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29F004BC-70PD | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 4 M (512 K X 8) BIT |
| MBM29F004BC-70PFTN | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 4 M (512 K X 8) BIT |
| MBM29F004BC-70PFTR | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 4 M (512 K X 8) BIT |
| MBM29F004BC-90PD | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 4 M (512 K X 8) BIT |
| MBM29F004BC-90PFTN | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:FLASH MEMORY CMOS 4 M (512 K X 8) BIT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。