參數(shù)資料
型號(hào)： MBM29LV002T-10
廠商： Fujitsu Limited
英文描述： 2M (256K ×8) Bit Flash Memory(2M (256K ×8)位 單5V 電源電壓閃速存儲(chǔ)器)
中文描述： 200萬(wàn)（256K × 8）位閃存（200萬(wàn)（256K × 8）位單5V的電源電壓閃速存儲(chǔ)器）
文件頁(yè)數(shù)： 14/45頁(yè)
文件大?。?/td> 406K
代理商： MBM29LV002T-10
14
MBM29LV002T
-10/-12
/MBM29LV002B
-10/-12
The device contains an Autoselect command operation to supplement traditional PROM programming method-
ology. The operation is initiated by writing the Autoselect command sequence into the command register. Fol-
lowing the command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read
cycle from address X001H returns the device code (MBM29LV002T = 40H, MBM29LV002B = C2H). (See Tables
3.1 and 3.2.)
All manufacturer and device codes will exhibit odd parity with the MSB (DQ
7
) defined as the parity bit.
Sector state (protection or unprotection) will be informed address X0002H.
Scanning the sector addresses (A
17
, A
16
, A
15
, A
14
, A
13
) while (A
10
, A
6
, A
1
, A
0
) = (0, 0, 1, 0) will produce a logical
“1” at device output DQ
0
for a protected sector.
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the autoselect command during the operation, execute it after writing Read/Reset command
sequence.
Byte Programming
The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two
“unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are
latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of
CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming.
Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide
further controls or timings. The device will automatically provide adequate internally generated program pulses
and verify the programmed cell margin.
The automatic programming operation is completed when the data on DQ
7
is equivalent to data written to this
bit at which time the device returns to the read mode and addresses are no longer latched. (See Table 7, Hardware
Sequence Flags.) Therefore, the device requires that a valid address to the device be supplied by the system
at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being
programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device (exceed timing limits), or result
in an apparent success according to the data polling algorithm but a read from read/reset mode will show that
the data is still “0”. Only erase operations can convert “0”s to “1”s.
Figure 17 illustrates the Embedded Program
TM
Algorithm using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Chip Erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the device will automatically program and verify the entire memory for an all zero
data pattern prior to electrical erase. The system is not required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates
when the data on DQ
7
is “1” (See Write Operation Status section.) at which time the device returns to read the
mode.
Figure 18 illustrates the Embedded Erase
TM
Algorithm using typical command strings and bus operations.
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