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參數(shù)資料
| 型號： | MBM29LV002T-10 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 2M (256K ×8) Bit Flash Memory(2M (256K ×8)位 單5V 電源電壓閃速存儲器) |
| 中文描述： | 200萬（256K × 8）位閃存（200萬（256K × 8）位單5V的電源電壓閃速存儲器） |
| 文件頁數(shù)： | 16/45頁 |
| 文件大?。?/td> | 406K |
| 代理商： | MBM29LV002T-10 |
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16
MBM29LV002T
-10/-12
/MBM29LV002B
-10/-12
Write Operation Status
Notes:
1. Performing successive read operations from the erase-suspended sector will cause DQ
2
to toggle.
2. Performing successive read operations from any address will cause DQ
6
to toggle.
3. Reading the byte address being programmed while in the erase-suspend program mode will indicate
logic “1” at the DQ
2
bit. However, successive reads from the erase-suspended sector will cause DQ
2
to
toggle.
4. DQ
0
and DQ
1
are reserve pins for future use.
5. DQ
4
is Fujitsu internal use only.
DQ
7
Data Polling
The MBM29LV002T/002B devices feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the device
will produce the complement of the data last written to DQ
7
. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ
7
. During the Embedded
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ
7
output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ
7
output. The flowchart
for Data Polling (DQ
7
) is shown in Figure 19.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
close to being completed, the MBM29LV002T/002B data pins (DQ
7
) may change asynchronously while the
output enable (OE) is asserted low. This means that the device is driving status information on DQ
7
at one instant
of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the
DQ
7
output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm
operation and DQ
7
has a valid data, the data outputs on DQ
0
to DQ
6
may be still invalid. The valid data on DQ
0
to DQ
7
will be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, or sector erase time-out. (See Table 7.)
See Figure 10 for the Data Polling timing specifications and diagrams.
Table 7 Hardware Sequence Flags
Status
DQ
7
DQ
6
DQ
5
DQ
3
DQ
2
In
Progress
Embedded Program Algorithm
DQ
7
Toggle
0
0
1
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
Erase
Suspended
Mode
Erase Suspend Read (Erase Suspended
Sector)
1
1
0
0
Toggle
(Note 1)
Erase Suspend Read (Non-Erase
Suspended Sector)
Data
Data
Data
Data
Data
Erase Suspend Program (Non-Erase
Suspended Sector)
DQ
7
Toggle
(Note 2)
0
0
1
(Note 3)
Exceeded
Time
Limits
Embedded Program Algorithm
DQ
7
Toggle
1
0
1
Program/Erase in Embedded Erase Algorithm
0
Toggle
1
1
N/A
Erase
Suspended
Mode
Erase Suspend Program (Non-Erase
Suspended Sector)
DQ
7
Toggle
1
0
N/A
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