參數(shù)資料
型號: MBM29LV080A-70PTV
廠商: FUJITSU LTD
元件分類: DRAM
英文描述: Low power audio DAC with PLL
中文描述: 1M X 8 FLASH 3V PROM, 70 ns, PDSO40
封裝: PLASTIC, TSOP1-40
文件頁數(shù): 26/49頁
文件大?。?/td> 400K
代理商: MBM29LV080A-70PTV
MBM29LV080A
-70/-90/-12
26
Write (Erase/Program) Operations
Parameter Symbols
(Continued)
Description
MBM29LV080A
Unit
JEDEC
Standard
-70
-90
-12
t
AVAV
t
WC
Write Cycle Time
Min.
70
90
120
ns
t
AVWL
t
AS
Address Setup Time
Min.
0
0
0
ns
t
WLAX
t
AH
Address Hold Time
Min.
45
45
50
ns
t
DVWH
t
DS
Data Setup Time
Min.
35
45
50
ns
t
WHDX
t
DH
Data Hold Time
Min.
0
0
0
ns
t
OES
Output Enable Setup Time
Min.
0
0
0
ns
t
OEH
Output Enable
Hold Time
Read
Min.
0
0
0
ns
Toggle and Data Polling
Min.
10
10
10
ns
t
GHWL
t
GHWL
Read Recover Time Before Write
(OE High to WE Low)
Min.
0
0
0
ns
t
GHEL
t
GHEL
Read Recover Time Before Write
(OE High to CE Low)
Min.
0
0
0
ns
t
ELWL
t
CS
CE Setup Time
Min.
0
0
0
ns
t
WLEL
t
WS
WE Setup Time
Min.
0
0
0
ns
t
WHEH
t
CH
CE Hold Time
Min.
0
0
0
ns
t
EHWH
t
WH
WE Hold Time
Min.
0
0
0
ns
t
WLWH
t
WP
Write Pulse Width
Min.
35
45
50
ns
t
ELEH
t
CP
CE Pulse Width
Min.
35
45
50
ns
t
WHWL
t
WPH
Write Pulse Width High
Min.
25
25
30
ns
t
EHEL
t
CPH
CE Pulse Width High
Min.
25
25
30
ns
t
WHWH1
t
WHWH1
Programming Operation
Typ.
8
8
8
μs
t
WHWH2
t
WHWH2
Sector Erase Operation (Note 1)
Typ.
1
1
1
s
t
EOE
Delay Time from Embedded Output Enable Max.
30
35
50
ns
t
VCS
V
CC
Setup Time
Min.
50
50
50
μs
t
VLHT
Voltage Transition Time (Note 2)
Min.
4
4
4
μs
t
WPP
Write Pulse Width (Note 2)
Min.
100
100
100
μs
t
OESP
OE Setup Time to WE Active (Note 2)
Min.
4
4
4
μs
t
CSP
CE Setup Time to WE Active (Note 2)
Min.
4
4
4
μs
t
RB
Recover Time From RY/BY
Min.
0
0
0
ns
t
RH
RESET Hold Time Before Read
Min.
200
200
200
ns
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