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參數(shù)資料
| 型號： | MBM29LV080A-70PTV |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | Low power audio DAC with PLL |
| 中文描述： | 1M X 8 FLASH 3V PROM, 70 ns, PDSO40 |
| 封裝： | PLASTIC, TSOP1-40 |
| 文件頁數(shù)： | 3/49頁 |
| 文件大?。?/td> | 400K |
| 代理商： | MBM29LV080A-70PTV |
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MBM29LV080A
-70/-90/-12
3
I
GENERAL DESCRIPTION
The MBM29LV080A is a 16M-bit, 3.0 V-only Flash memory organized as 1M bytes of 8 bits each. The 1M bytes
of data is divided into 32 sectors of 64K bytes of flexible erase capability. The 8 bits of data will appear on DQ
0
to DQ
7
. The MBM29LV080A is offered in a 40-pin TSOP (I) package. The device is designed to be programmed
in-system with the standard system 3.0 V V
CC
supply. 12.0 V V
PP
and 5.0 V V
CC
are not required for write or erase
operations. The device can also be reprogrammed in standard EPROM programmers.
The standard MBM29LV080A offers access times of 70 ns and 120 ns, allowing operation of high-speed micro-
processors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
The MBM29LV080A is pin and command set compatible with JEDEC standard E
2
PROMs. Commands are written
to the command register using standard microprocessor write timings. Register contents serve as input to an
internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the device is similar
to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29LV080A is programmed by executing the program command sequence. This will invoke the Embed-
ded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and
verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase
is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm
which is an internal algorithm that automatically preprograms the array if it is not already programmed before
executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies
proper cell margins.
Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29LV080A is erased when shipped from the factory.
Fujitsu has implemented an Erase Suspend feature that enables the user to put erase on hold for any period of
time to read data from or program data to a mom-busy sector. Thus, true background erase can be achieved.
The device features single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase cycle has been
comleted, the device internally resets to the read mode.
The MBM29LV080A also has a hardware RESET pin. When this pin is driven low, execution of any Embedded
Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the
read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during
the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read
mode and will have erroneous data stored in the address locations being programmed or erased. These locations
need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up
firmware from the Flash memory.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability, and cost effectiveness. The MBM29LV080A memory electrically erases all bits within
a sector simultaneously via Fowler-Nordhiem tunneling. The bytes are programmed one byte at a time using
the EPROM programming mechanism of hot electron injection.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MBM29LV080A-90PTR | Low power audio DAC |
| MBM29LV080A-90PTV | Low power audio DAC |
| MBM29LV080A-12PTV | 8M (1M x 8) BIT |
| MBM29LV080A-70 | 8M (1M x 8) BIT |
| MBM29LV080A-90 | 8M (1M x 8) BIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MBM29LV080A-90 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8M (1M x 8) BIT |
| MBM29LV080A-90PTR | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8M (1M x 8) BIT |
| MBM29LV080A-90PTV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8M (1M x 8) BIT |
| MBM29LV160B | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M xⅴ 8/1M x 16) BIT |
| MBM29LV160B-12 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:16M (2M xⅴ 8/1M x 16) BIT |
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