參數(shù)資料
型號： MBM29LV652UE
廠商： Fujitsu Limited
英文描述： 64M (4M X 16) BIT
中文描述： 64M號（4米× 16）位
文件頁數(shù)： 29/58頁
文件大小： 571K
代理商： MBM29LV652UE
MBM29LV652UE-
90/12
29
RY/BY
Ready/Busy
The MBM29LV652UE provide a RY/BY open-drain output pin as a way to indicate to the host system that the
Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are busy
with either a program or erase operation. If the output is high, the devices are ready to accept any read/write or
erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands. If the MBM29LV652UE is placed in an Erase Suspend mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. Refer to Figures 12 and 13 for a detailed timing diagram. The RY/BY
pin is pulled high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to V
CC
.
Data Protection
The MBM29LV652UE is designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the devices automatically
reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The
devices also incorporate several features to prevent inadvertent write cycles resulting form V
CC
power-up and
power-down transitions or system noise.
Low V
CC
Write Inhibit
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less
than V
LKO
(min). If V
CC
< V
LKO
, the command register is disabled and all internal program/erase circuits are disabled.
Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the V
CC
level
is greater than V
LKO
. It is the users responsibility to ensure that the control pins are logically correct to prevent
unintentional writes when V
CC
is above V
LKO
(Min.).
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = V
IL
, CE = V
IH
, or WE = V
IH
. To initiate a write, CE and WE must
be a logical zero while OE is a logical one.
Power-up Write Inhibit
Power-up of the devices with WE = CE = V
IL
and OE = V
IH
will not accept commands on the rising edge of WE.
The internal state machine is automatically reset to read mode on power-up.
相關PDF資料
PDF描述
MBM29LV652UE-12 64M (4M X 16) BIT
MBM29LV652UE-90 64M (4M X 16) BIT
MBM29LV652UE90PBT 64M (4M X 16) BIT
MBM29LV800BA 8M (1M X 8/512K X 16) BIT
MBM29LV800BA-90 LED Lamp; Bulb Size:T-1 3/4; LED Color:Amber; Luminous Intensity:2000ucd; Viewing Angle:20 ; Forward Current:20mA; Forward Voltage:2.1V; Operating Temperature Range:-25 C to +85 C; Color:Amber; Leaded Process Compatible:Yes RoHS Compliant: Yes
相關代理商/技術參數(shù)
參數(shù)描述
MBM29LV652UE-12 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:64M (4M X 16) BIT
MBM29LV652UE-90 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:64M (4M X 16) BIT
MBM29LV652UE90PBT 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:64M (4M X 16) BIT
MBM29LV800BA 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8M (1M X 8/512K X 16) BIT
MBM29LV800BA-12 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8M (1M X 8/512K X 16) BIT
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