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參數(shù)資料
| 型號： | MC-4516DC72 |
| 廠商： | NEC Corp. |
| 英文描述： | 16 M-Word By 72-Bit Synchronous Dynamic RAM Module(同步動態(tài)RAM 模塊) |
| 中文描述： | 16米，由72個字位同步動態(tài)隨機存儲器模塊（同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 211K |
| 代理商： | MC-4516DC72 |
12
MC-4516DC72
Relationship between Frequency and Latency
[ MC-4516DC72-A10, 4516DC72-A12 ]
Speed version
-A10
-A12
Clock cycle time [ns]
10
15
12
18
Frequency [MHz]
100
67
83
55
/CAS latency + 1 cycle
3 + 1
2 + 1
3 + 1
2 + 1
[t
RCD
]
3
2
3
2
/RAS latency (/CAS latency + [t
RCD
])
7
5
7
5
[t
RC
]
10
7
9
6
[t
RAS
]
6
4
6
4
[t
RRD
]
2
2
2
2
[t
RP
]
3
2
3
2
[t
DPL
]
0
0
0
0
[t
DAL
]
4
2
4
2
Remark
All internal signals (A0
-
A11, BA0, BA1, /CS0, /CS1, CKE0, CKE1, /RAS, /CAS, /WE, DQM) from register
are delayed by one cycle. Therefore, DQ is delayed by one cycle.
[ MC-4516DC72-A10B ]
Speed version
-A10B
Clock cycle time [ns]
10
15
Frequency [MHz]
100
67
/CAS latency + 1 cycle
3 + 1
2 + 1
[t
RCD
]
3
2
/RAS latency (/CAS latency + [t
RCD
])
7
5
[t
RC
]
9
6
[t
RAS
]
6
4
[t
RRD
]
2
2
[t
RP
]
3
2
[t
DPL
]
0
0
[t
DAL
]
3
2
Remark
All internal signals (A0
-
A11, BA0, BA1, /CS0, /CS1, CKE0, CKE1, /RAS, /CAS, /WE, DQM) from register
are delayed by one cycle. Therefore, DQ is delayed by one cycle.
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| MC-4532DA727 | 32M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE |
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