- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9262 > MC100EP195FAR2 (ON Semiconductor)IC DELAY LINE 1024TAP 32-LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | MC100EP195FAR2 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 100EP |
| 標(biāo)片/步級(jí)數(shù)： | 1024 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 2.2ns |
| 接頭增量： | 10ps |
| 可用的總延遲： | 2.2ns ~ 12.2ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-LQFP（7x7） |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | MC100EP195FAROSCT |
Semiconductor Components Industries, LLC, 2009
April, 2009 Rev. 18
1
Publication Order Number:
MC10EP195/D
MC10EP195, MC100EP195
3.3V ECL Programmable
Delay Chip
The MC10/100EP195 is a Programmable Delay Chip (PDC)
designed primarily for clock deskewing and timing adjustment. It
provides variable delay of a differential NECL/PECL input transition.
The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 3. The delay
increment of the EP195 has a digitally selectable resolution of about
10 ps and a net range of up to 10.2 ns. The required delay is selected by
the 10 data select inputs D[9:0] values and controlled by the LEN
(pin 10). A LOW level on LEN allows a transparent LOAD mode of
real time delay values by D[9:0]. A LOW to HIGH transition on LEN
will LOCK and HOLD current values present against any subsequent
changes in D[10:0]. The approximate delay values for varying tap
numbers correlating to D0 (LSB) through D9 (MSB) are shown in
Because the EP195 is designed using a chain of multiplexers it has a
fixed minimum delay of 2.2 ns. An additional pin D10 is provided for
controlling Pins 14 and 15, CASCADE and CASCADE, also latched
by LEN, in cascading multiple PDCs for increased programmable
range. The cascade logic allows full control of multiple PDCs.
Switching devices from all “1” states on D[0:9] with SETMAX LOW
to all “0” states on D[0:9] with SETMAX HIGH will increase the
delay equivalent to “D0”, the minimum increment.
Select input pins D[10:0] may be threshold controlled by
combinations of interconnects between VEF (pin 7) and VCF (pin 8)
for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input
levels, leave VCF and VEF open. For ECL operation, short VCF and
VEF (Pins 7 and 8). For LVTTL level operation, connect a 1.5 V
supply reference to VCF and leave open VEF pin. The 1.5 V reference
voltage to VCF pin can be accomplished by placing a 2.2 kW resistor
between VCF and VEE for a 3.3 V power supply.
The VBB pin, an internally generated voltage supply, is available to
this device only. For singleended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
Maximum Input Clock Frequency >1.2 GHz Typical
Programmable Range: 0 ns to 10 ns
Delay Range: 2.2 ns to 12.2 ns
10 ps Increments
PECL Mode Operating Range:
VCC = 3.0 V to 3.6 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = 3.0 V to 3.6 V
Open Input Default State
Safety Clamp on Inputs
A Logic High on the EN Pin Will Force Q to Logic
Low
D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL
Inputs
VBB Output Reference Voltage
PbFree Packages are Available
32
1
LQFP32
FA SUFFIX
CASE 873A
MARKING
DIAGRAM*
XXX
= 10 or 100
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G = PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
MCXXX
EP195
AWLYYWWG
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
ORDERING INFORMATION
QFN32
MN SUFFIX
CASE 488AM
32
1
MCXXX
EP195
AWLYYWWG
G
1
(Note: Microdot may be in either location)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-B64-MY-F1 | CONVERTER MOD DC/DC 48V 50W |
| VE-J6R-MZ | CONVERTER MOD DC/DC 7.5V 25W |
| MC10E195FN | IC DELAY LINE 128TAP 28-PLCC |
| MC100E195FN | IC DELAY LINE 128TAP 28-PLCC |
| SY10E196JZ | IC DELAY LINE 7TAP 28-PLCC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100EP195FAR2G | 功能描述:延遲線/計(jì)時(shí)元素 3.3V/5V ECL Programmable Delay RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP195MNG | 功能描述:延遲線/計(jì)時(shí)元素 BBG ECL PROG DELAY CHIP RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP195MNR4G | 功能描述:延遲線/計(jì)時(shí)元素 BBG ECL PROG DELAY CHIP RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時(shí)間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP196 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3V ECL Programmable Delay Chip with FTUNE |
| MC100EP196_06 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3V ECL Programmable Delay Chip with FTUNE |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。