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參數(shù)資料
| 型號： | MC100SX1451FI100FI |
| 廠商： | Motorola, Inc. |
| 英文描述： | Current-Limited, Power-Distribution Switches 8-MSOP-PowerPAD -40 to 85 |
| 中文描述： | AUTOBAHNE⑩⑩SPANCEIVERE |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 197K |
| 代理商： | MC100SX1451FI100FI |
MC100SX1451FI100
MOTOROLA
ECLinPS and ECLinPS Lite
DL140 — Rev 3
6
of 100MByte/s, a new data word is transferred approximately
every 40ns (32 data bits + 4 synchronization bits = 36 bits *
1.1ns/bit). For this case, the timeout timer runs for
approximately 160ns. The timeout timer is re–started every
time a new serial word transmission begins.
The transmit timeout timer serves two functions. It allows
the termination of block data transfers without the need for
explicit external control. After the last word in a data block is
written into the device, the timeout timer will expire and the
device will return to the idle state. More importantly, it allows
the AutoBahn to support a broad range of data transfer rates.
If a hardware design application only needs capacity to
transfer data at 60MByte/s, the AutoBahn will automatically
burst the data out at 100MByte/sec and insert pauses in the
serial data stream to accommodate the slower parallel data
transfer rate. This means the user can tailor the design of the
parallel memory interface to meet the needs of the
application, while still taking advantage of the performance of
the AutoBahn.
Since the AutoBahn only has one level of elastic storage,
the receiver memory interface must be able to support the
same transfer rate as the transmitter.
Receive Mode
When the AutoBahn is operating in receive mode it strips
off the timing information and clocks the data into the serial
register. When the register is full, it transfers the data into the
parallel data register and asserts the FULL signal pin to
indicate the presence of data. The interface hardware
detects the presence of new data and reads out the content
of the data register. In receive mode, a timeout timer is also
employed to handle the end of data transfer termination. The
receive timeout timer operates in the same manner as the
transmit timeout timer. Every time new data is received, the
timeout timer is re–started. If no data is received, the timeout
timer will expire and the part will return to the idle state.
Typical data transmission waveforms are shown in Figure 3
and Figure 4.
Figure 3. Transmit and Receive Timing for a Single 32–Bit Longword Transmissions
REGSEL
D00:D31
R/W
STRB
FULL
SER
BUSY
WRITE DATA
TIMEOUT DELAY
D31
SYNC D0
D1
D2
D3
CUTOFF
CUTOFF
T
REGSEL
D00:D31
R/W
STRB
FULL
SER
BUSY
READ DATA
TIMEOUT DELAY
D31
CUTOFF
CUTOFF
R
SYNC D0
D1
D2
D3
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