參數(shù)資料
型號(hào): MC10107L
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Triple 2-Input Exclusive OR/Exclusive NOR Gate
中文描述: 10K SERIES, TRIPLE 2-INPUT XOR/XNOR GATE, CDIP16
封裝: CERAMIC, DIP-16
文件頁數(shù): 1/5頁
文件大?。?/td> 104K
代理商: MC10107L
SEMICONDUCTOR TECHNICAL DATA
3–30
REV 5
Motorola, Inc. 1996
3/93
The MC10107 is a triple–2 input exclusive OR/NOR gate.
PD= 40 mW typ/gate (No Load)
tpd= 2.8 ns typ
tr, tf= 2.5 ns typ (20%–80%)
LOGIC DIAGRAM
VCC1= PIN 1
VCC2= PIN 16
VEE= PIN 8
15
13
14
9
7
4
5
12
10
11
3
2
3 = (4
5) + (4
5)
2 = (4
5) + (4
5)
DIP
PIN ASSIGNMENT
VCC1
AOUT
AOUT
AIN
AIN
*NC
BIN
VEE
VCC2
CIN
CIN
COUT
COUT
BOUT
BOUT
BIN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
*NC = No Connection
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
L SUFFIX
CERAMIC PACKAGE
CASE 620–10
P SUFFIX
PLASTIC PACKAGE
CASE 648–08
FN SUFFIX
PLCC
CASE 775–02
相關(guān)PDF資料
PDF描述
MC10107P Triple 2-Input Exclusive OR/Exclusive NOR Gate
MC10109FN Replaced by SN54LS132 : Quadruple 2-Input Positive-NAND Schmitt Triggers 14-CDIP -55 to 125
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MC10109L Replaced by SN54LS132 : Quadruple 2-Input Positive-NAND Schmitt Triggers 14-CDIP -55 to 125
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