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參數(shù)資料
| 型號： | MC100SX1451FI100FI |
| 廠商： | Motorola, Inc. |
| 英文描述： | Current-Limited, Power-Distribution Switches 8-MSOP-PowerPAD -40 to 85 |
| 中文描述： | AUTOBAHNE⑩⑩SPANCEIVERE |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 197K |
| 代理商： | MC100SX1451FI100FI |
MC100SX1451FI100
ECLinPS and ECLinPS Lite
DL140 — Rev 3
9
MOTOROLA
CONTROL AND ERROR REGISTER BIT DEFINITIONS
Figure 9. Control and Error Register Definitions
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CLEAR
FACTORY TEST
FACTORY TEST
16–/32–BIT MODE
RESERVED
WRITE:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CLEAR
FACTORY TEST
FACTORY TEST
16–/32–BIT MODE
RESERVED
READ:
FACTORY
TEST
FACTORY TEST
IGNORE TIMEOUT
SYNC BIT ERROR
WORD MISSING ERROR
ERROR
CONTROL
FACTORY TEST
IGNORE TIMEOUT
OVERWRITE ERROR
FACTORY
TEST
Clear
Asserting this bit clears the internal control logic and
terminates any transmit or receive activity. To remove the
Clear condition, this bit must be set to a logic ‘H’ which sets
the chip into the Idle mode.
H
Normal Operation
L
Clear
16/32 Bit Mode
This bit defines the data width on the host interface. This
feature allows the AutoBahn chip to be used in systems with
either 16–bit or 32–bit data width without the need for
additional interface hardware. In 16–bit mode, the data bus
used is D00 – D15.
H
32–bit data width
L
16–bit data width
Factory Test
These bits are used by the manufacturer for testing the
product. It must be set to a logic ‘H’ state for proper operation.
H
Normal Operation
Ignore Timeout
This bit is used to disable the timeout timer for the
transmitter. The purpose of this bit is to allow for the
establishment of permanent or temporary dedicated links.
When this bit is asserted, the timeout timer will be ignored by
the PISO Control Logic. This bit only needs to be set in the
transmitting AutoBahn chip. To exit this mode, the Control
Register must be accessed, and the field must be
de–asserted.
H
Normal Operation
L
Disable Timeout
Overwrite Error Flag
This bit will be set if the data in the parallel register is
overwritten. This can occur in Receive mode if data is not
read from the parallel register in a timely manner. The
overwrite error does not occur in idle mode.
H
Overwrite
L
No Overwrite
Word Missing Error
This bit will be asserted if the second half of a 32–bit
transfer is not completed before the time out timer expires.
This can occur if the transmitter fails to complete the transfer.
This field will be asserted only after the timeout timer expires.
H
Word Missing Error
L
No Error
SYNC Bit Missing Error
This bit will be asserted if the AutoBahn detects that a
SYNC bit has not been received at the proper time by the
PISO Control Logic. If this bit has been asserted then the
data has been corrupted.
H
SYNC Bit Missing Error
L
No Error
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