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參數(shù)資料
| 型號： | MC10E197FN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 光電元器件 |
| 英文描述： | DATA SEPARATOR |
| 中文描述： | PULSE DETECTOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 217K |
| 代理商： | MC10E197FN |
MC10E197
2–5
MOTOROLA
ECLinPS and ECLinPS Lite
DL140 — Rev 4
Idle Mode
In the absence of data or when the drive is writing to the disk,
PLL servoing is accomplished by pulling the read enable line
(RDEN) low and providing a reference clock via the REFCLK
pins. The condition whereby RDEN is low selects the
Phase/Frequency detector (Figure 1) and the 10E197 is said
to be operating in the “idle mode”. In order to function as a
frequency detector the input waveform must be periodic. The
pump up and pump down pulses from the Phase/Frequency
detector will have the same frequency, phase and pulse width
only when the two clocks that are being compared have their
positive edges aligned and are of the same frequency.
As with the data phase detector, by using suitable external
filter circuitry, a VCO input control signal can be generated by
inverting the pump down signal, summing the inverted signal
with the pump up signal and averaging the result. The polarity
of this control signal is defined as zero when all positive edges
of both clocks are coincident. For the case in which the
frequencies of the two clocks are the same but the clock edges
of the reference clock are slightly advanced with respect to the
VCO clock, the control clock is defined to have a positive
polarity. A control signal with negative polarity occurs when
the edges of the reference clock are delayed with respect to
those of the VCO. If the frequencies of the two clocks are
different, the clock with the most edges per unit time will initiate
the most pulses and the polarity of the detector will reflect the
frequency error. Thus, when the reference clock is high in
frequency than the VCO clock the polarity of the control signal
is positive; whereas a control signal with negative polarity
occurs when the frequency of the reference clock is lower than
the VCO clock.
Phase-Lock Loop Theory
Introduction
Phase lock loop (PLL) circuits are fundamentally feedback
systems used to synchronize the frequency of an oscillator to
an incoming signal. In addition to frequency synchronization,
the PLL circuitry is designed to minimize the phase difference
between the system input and output signals. A block diagram
of a feedback control system is shown in Figure 1.
where:
A(s) is the product of the feed-forward transfer functions.
Figure 1. Feedback System
Xi(s)
Xo(s)
A(s)
β
(s)
+
–
Xe(s)
R
β
(s) is the product of the feedback transfer functions.
The transfer function for this closed loop system is
Xo(s)
Xi(s)
=
A(s)
1 + A(s)
β
(s)
Typically, phase lock loops are modeled as feedback
systems connected in a unity feedback configuration (
β
(s)=1)
with a phase detector, a VCO (voltage controlled oscillator),
and a loop filter in the feed-forward path, A(s). Figure 2
illustrates a phase lock loop as a feedback control system in
block diagram form.
LOOP FILTER
F(s)
Fi
Fo
PHASE
DETECTOR
Kf
VCO
Ko
s
Figure 2. Phase Lock Loop Block Diagram
The closed loop transfer function is:
Xo(s)
Xi(s)
=
K
φ
Ko
s
F(s)
Ko
s
1 + K
φ
F(s)
where:
K
φ
=
Ko=
the phase detector gain.
the VCO gain. Since the VCO introduces a
pole at the origin of the s-plane, Ko is divided
by s.
F(s) = the transfer function of the loop filter.
The 10E197 is designed to implement the phase detector
and VCO functions in a unity feedback loop, while allowing the
user to select the desired filter function.
Gain Constants
As mentioned, each of the three sections in the phase lock
loop block diagram has an associated open loop gain
constant. Further, the gain constant of the filter circuitry is
composed of the product of three gain constants, one for each
filter subsection. The open loop gain constant of the
feed-forward path is given by
Kol = K
φ
* Ko * K1 * Kl * Kd
and obtained by performing a root locus analysis.
eqt. 1
Phase Detector Gain Constant
The gain of the phase detector is a function of the operating
mode and the data pattern. The 10E197 provides data
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| MC10E211FN | 功能描述:時鐘驅(qū)動器及分配 5V ECL 1:6 Diff RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC10E211FNG | 功能描述:時鐘驅(qū)動器及分配 5V ECL 1:6 Diff Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC10E211FNR2 | 功能描述:時鐘驅(qū)動器及分配 5V ECL 1:6 Diff RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MC10E211FNR2G | 功能描述:時鐘驅(qū)動器及分配 5V ECL 1:6 Diff Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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