參數(shù)資料
型號: MC13226V
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA99
封裝: 9.50 X 9.50 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, LGA-99
文件頁數(shù): 18/54頁
文件大?。?/td> 490K
代理商: MC13226V
MC1322x Technical Data, Rev. 1.3
Freescale Semiconductor
25
5.7
Synchronous Serial Interface (SSI) Module
The MC1322x provides a versatile Synchronous Serial Interface (SSI) which is a full-duplex, serial port
that allows communication with a variety of serial devices. These serial devices can be digital signal
processors (DSPs), MCUs, peripherals, popular industry audio CODECs, and devices that implement the
Inter-Integrated Circuit sound bus standard (I2S).
The SSI typically transfers samples in a periodic manner and it consists of independent transmitter and
receiver sections with common clock generation and frame synchronization. The external signals include
the bit clock (SSI_BITCK), frame sync (SSI_FSYN), RX data (SSI_RX), and TX data (SSI_TX). The SSI
has the following basic operating modes all with synchronous protocol:
Normal mode — The simplest SSI mode transfers data in one time slot per frame
Network mode — Creates a Time Division Multiplexed (TDM) network, such as a TDM CODEC
network or a network of DSPs
Gated Clock mode — Connects to SPI-type interfaces on MCUs or external peripheral chips
With its multi-modes, the SSI can be programmed for two very useful functions:
A second SPI port augmenting the MC1322x SPI module
I2S interface - the SSI is capable of generating the required clock frequencies and data format to
drive a serial stereo audio DAC
The SSI includes the following features:
Synchronous transmit and receive sections with shared internal/external clocks and frame syncs,
operating in Master or Slave mode.
Normal mode operation using frame sync
Network mode operation allowing multiple devices to share the port with as many as thirty-two
time slots
Gated Clock mode operation requiring no frame sync
SSI clock source is Peripheral Clock (typically 24 MHz); maximum SSI transfer rate is 6.0 MHz
Separate Transmit and Receive FIFOs. Each of which is 8x24 bits
Programmable data interface modes including I2S, LSB, MSB aligned
Programmable word length (8, 10, 12, 16, 18, 20, 22 or 24 bits)
Program options for frame sync and clock generation
Programmable I2S modes (Master, Slave)
Programmable internal clock divider
Time Slot Mask Registers for reduced CPU overhead (for Tx and Rx both)
SSI power-down feature
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