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參數(shù)資料
| 型號(hào)： | MC145173DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | XO, clock |
| 英文描述： | Dual-Band PLL Frequency Synthesizer with ADC and Frequency Counter |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 130 MHz, PDSO24 |
| 封裝： | SOG-24 |
| 文件頁數(shù)： | 17/33頁 |
| 文件大?。?/td> | 277K |
| 代理商： | MC145173DW |
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MC145173
17
MOTOROLA
A REGISTER BITS
EOC
End of Conversion (A7)
The end of conversion bit is set high when the analog–to–
digital conversion is complete. This high level indicates that
the A/D conversion value read via the serial port is valid.
EOC is cleared low when the I SMPL bit in the C register is
cleared low.
IN C
Input C Level (A6)
In C indicates the state of the Input C pin. A high level on
the Input C pin causes the In C bit to be high. A low level on
the pin causes a low level to be read on In C. The digital val-
ue is stored at the falling edge of ENB on the read cycle.
ADC CONVERSION VALUE
A/D Conversion Value (A5 – A0)
These bits contain the analog–to–digital conversion result
in binary format. A5 is the MSB of the value; A0 is the LSB.
IN D
Input D Level (A#)
In D indicates the state of the Input D pin. A high level on
the Input D pin causes the In D bit to be high. A low level on
the pin causes a low level to be read on In D. The digital val-
ue is stored at the falling edge of ENB on the read cycle.
A 9– or 16–bit shift must be used to read the In D bit from
the A register. Optionally, the In D bit may be read from the F
register.
NOTE: This is a read–only register.
1
2
3
4
5
6
7
8
ENB
CLK
Dout
9
10
11
12
13
14
15
16
A7
A6
A5
A4
A3
A2
A1
A0
A#
x
x
x
x
x
x
x
EOC
IN C
ADC
CONVERSION
VALUE
IN D
DON’T CARE
1
2
3
4
5
6
7
8
ENB
CLK
Dout
9
A7
A6
A5
A4
A3
A2
A1
A0
A#
MSB
MSB
EOC
IN C
ADC
CONVERSION
VALUE
IN D
ENB
CLK
Dout
1
2
3
4
5
6
7
8
A7
A6
A5
A4
A3
A2
A1
A0
EOC
IN C
ADC
CONVERSION
VALUE
MSB
Figure 21. A Register Formats (8, 9, or 16 Clock Cycles May Be Used)
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