參數(shù)資料
型號： MC145173DW
廠商： MOTOROLA INC
元件分類： XO, clock
英文描述： Dual-Band PLL Frequency Synthesizer with ADC and Frequency Counter
中文描述： PLL FREQUENCY SYNTHESIZER, 130 MHz, PDSO24
封裝： SOG-24
文件頁數(shù)： 3/33頁
文件大?。?/td> 277K
代理商： MC145173DW
MC145173
3
MOTOROLA
ABSOLUTE MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin
Vout
Iin
Iout
IDD
PD
Tstg
TL
DC Supply Voltage
– 0.5 to +
6.0
V
DC Input Voltage
–
0.5 to VDD + 0.5
– 0.5 to VDD + 0.5
±
10
V
DC Output Voltage
V
DC Input Current, per Pin
mA
DC Output Current, per Pin
±
20
mA
DC Supply Current, VDD and VSS Pins
Power Dissipation, per Package
±
30
mA
300
mW
Storage Temperature
–
65 to +
150
°
C
Lead Temperature, 1 mm from Case
for 10 seconds
260
°
C
* Maximum Ratings are those values beyond which damage to the device may occur. Func-
tional operation should be restricted to the limits in the Electrical Characteristics tables or
Pin Descriptions section.
DC ELECTRICAL CHARACTERISTICS
(VDD = 4.5 to 5.5 V, Voltages Referenced to VSS, TA = –40 to +85
°
C)
Symbol
Parameter
Test Condition
Guaranteed
Limit
Unit
VIL
VIH
VIL
Maximum Low–Level Input Voltage (Din, CLK, ENB)
Minimum High–Level Input Voltage (Din, CLK, ENB)
Maximum Low–Level Input Voltage
(Input D, HF IFin, VHF IFin, HFin, VHFin, OSCin)
Minimum High–Level Input Voltage
(Input D, HF IFin, VHF IFin, HFin, VHFin, OSCin)
Minimum Hysteresis Voltage (CLK, ENB)
0.25 x VDD
0.65 x VDD
0.3 x VDD
V
V
dc coupled
V
VIH
dc coupled
0.7 x VDD
V
VHys
VTH
0.3
V
Threshold Voltage (INPUT C)
Vin Ramped Down from VDD
0.28 x VDD
to
0.38 x VDD
0.1
V
VOL
Maximum Low–Level Output Voltage
(Dout, OUTPUT A, OUTPUT B, OUTPUT C, OUTPUT D, HF PDout)
Minimum High–Level Output Voltage
(Dout, OUTPUT B, OUTPUT C, OUTPUT D, HF PDout, REFout)
Minimum Low–Level Output Current (HF PDout)
Minimum High–Level Output Current (HF PDout)
Minimum Low–Level Output Current (Dout)
Minimum High–Level Output Current (Dout)
Minimum Low–Level Output Current
(OUTPUT B, OUTPUT C, OUTPUT D)
Iout = 20
μ
A
V
VOH
Iout = –20
μ
A
VDD – 0.1
V
IOL
IOH
IOL
IOH
IOL
Vout = 0.4 V
Vout = VDD – 0.4 V
Vout = 0.4 V
Vout = VDD – 0.4 V
Vout = 1.0 V
0.36
mA
– 0.36
mA
1.6
mA
– 1.6
mA
2.0
mA
IOH
Minimum High–Level Output Current
(OUTPUT B, OUTPUT C, OUTPUT D)
Vout = VDD – 1.0 V
– 2.0
mA
IOL
IOH
Iin
Minimum Low–Level Output Current (OUTPUT A)
Vout = 1.0 V
Vout = VDD – 1.0 V
Vin = VDD or VSS,
Device NOT in Standby**
2.0
mA
Minimum High–Level Output Current (REFout)
Maximum Input Leakage Current
(Din, CLK, ENB, OSCin, INPUT A, INPUT B, INPUT C, INPUT D)
Maximum Input Current
(HFin, VHFin, HF IFin, VHF IFin)
Maximum Output Leakage Current (HF PDout)
– 1.75
±
1.0
mA
μ
A
Iin
Vin = VDD or VSS,
Device NOT in Standby
±
120
μ
A
IOZ
Vout = VDD or VSS,
Output in High–Impedance State
±
200
nA
IOZ
Maximum Output Leakage Current (VHF PDout)
Vout = 1.75 or VDD – 1.5 V,
Output in High–Impedance State
±
200
nA
IOZ
Maximum Output Leakage Current (REFout, OUTPUT A, Dout)
Vout = VDD or VSS,
Output in High–Impedance State
±
2
μ
A
Continued on next page.
** While in Standby, the OSCin pin is pulled low by a weak on–chip FET.
This device contains protection circuitry to
guard against damage due to high static volt-
ages or electric fields. However, precautions
must be taken to avoid applications of any volt-
age higher than maximum rated voltages to
this high–impedance circuit. For proper opera-
tion, Vin and Vout should be constrained to the
range VSS
≤
(Vin or Vout)
≤
VDD.
For proper termination of unused pins, see
the Pin Descriptions section.
相關(guān)PDF資料
PDF描述
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