參數(shù)資料
型號: MC145202-1
廠商: Motorola, Inc.
英文描述: PLL Frequency Synthesizer(2.0GHz PLL頻率合成器)
中文描述: 鎖相環(huán)頻率合成器(2.0GHz的鎖相環(huán)頻率合成器)
文件頁數(shù): 22/23頁
文件大小: 270K
代理商: MC145202-1
M
2
M
S
1
2
7
8
9
15
16
17
23
24
25
R Register Bits of Device #2
in Figure 22
R Register Bits of Device #1
in Figure 22
R15
R14
R8
R7
R0
X
X
R15
31
32
33
39
40
R8
R7
R0
Note 1 Note 2
F
ENB
CLK
Din
1. At this point, bits R13, R14 and R15 are stored and sent to the ‘‘OSC or 4–Stage Divider” block in the Block Diagram. Bits R0 through
R12 are loaded into the first buffer in the double–buffered section of the R register. Therfore, the R counter divide is not altered yet and
retains the previous ratio loaded. The C and A registers are not affected.
2. Optional load pulse. At this point, the bits R0 through R12 are transfered to the second buffer of the R register. The R counter begins dividing
by the new ratio after completing the rest of the present count cycle. CLK must be low during the ENB pulse, as shown. The C and A registers
are not affected. The first buffer of the R register is not affected. Also, see note of Figure 24 for an alternate method of loading the second
buffer in the R register.
Notes Applicable to Each Device:
Figure 25. Accessing the R Registers of Two Cascaded
MC145193 or MC145202–1 Devices
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