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參數(shù)資料
| 型號： | MC145230 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器) |
| 中文描述： | 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 66/71頁 |
| 文件大?。?/td> | 906K |
| 代理商： | MC145230 |
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MC145225 MC145230
66
MOTOROLA RF/IF DEVICE DATA
In summary, $88EA60 is serially transferred (BitGrabber
access). The N register access also causes double–buffer
transfers of Hr to R and Hn to N .
Step 6: Load the C Register
Now that legitimate divide ratios are programmed for the
counters, the main loop may be activated. Thus, the PD float
bit C4 is now programmed to 0. The standby bits are
unchanged: C2 = C1 = C0 = 0. Bit C5 could be used to control
Output C to either a low level or high impedance; for a low
level, C5 = 0. Whenever an external reference is utilized, bit
C6 must be 1. Bit C7 may be used to control Output A to a low
or high level because it is selected as “port expander” by bit
R 21 and R 20; for a low level, C7 = 0.
In summary, $40 is serially transferred (BitGrabber
access). This causes the main loop to tune to 1.8 GHz, the
secondary loop to tune to 200 MHz, and both the Output A
and Output C pins to be forced low.
The device is now initialized.
8C. PROGRAMMING WITHOUT ADAPT
Tuning the Top of the Band
After initializing the device via steps 1 through 6 in Section
8B, the only register that needs to be loaded to tune the main
loop is the N register.
For this example, tuning the upper end of the band
(2.1 GHz) requires that the 30 kHz at the phase/frequency
detector be multiplied up to 2.1 GHz. This is a loop
multiplying factor of 70,000. This value is converted to
$11170 and is loaded for bits N17 to N0. Bits N23 to N18 are
not changed and are programmed as indicated in Section 8B,
step 5.
In summary, $891170 is transferred to tune the main loop.
No other registers are loaded.
Tuning Other Channels
Tuning other channels for the main loop, while keeping the
secondary loop at a constant frequency, only requires
programming the N register. See Table 22 for example
frequencies.
Table 22. Main Loop Tuning Examples
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8D. PROGRAMMING UTILIZING HORSESHOE WITH
ADAPT
Introduction
A unique adapt feature can be used with the MC145225 or
MC145230 when conventional tuning cannot meet the
lock–time requirements of a system and the annoying spurs
or noise cannot be tolerated from a fractional–N scheme. The
adapt feature is available on the main loop only.
For adapt, a timer is engaged which causes an internal
data update of the R and N registers to be delayed. The IC
supports the Horseshoescheme for adapt by allowing a
fairly–close quickly–tuned approximatefrequency to be
tuned, followed by the tuning of the exactfrequency. Two sets
of R and N data are sent to the device. The first set {R1, N1}
is for tuning the approximate frequency. The second set {R2,
N2} is for tuning the exact frequency. Use of the timer delays
the transfer of {R2, N2} until a programmed interval has
elapsed. In addition, after the interval has elapsed, the main
loop control switches from PDout–Hi to PDout–Lo.
Tuning Near the Top of the Band
Continuing the example, after initializing the device via
steps 1 through 6 in Section 8B, Horseshoe with adapt can
be used to tune the main loop to obtain fast frequency jumps.
Use of the BitGrabber access is recommended to minimize
the number of serial data clocks required for sending the four
“words”.
In this example, the first phase of adapt utilizes
approximate tuning with the phase/frequency detector
running at 4x the step size. Therefore, the approximate
tuning runs the detector at about 120 kHz. The second
phase, with exact tuning, runs the detector at 30 kHz.
Horseshoe with adapt requires that two data sets be serially
sent to the device for every frequency tuned. The first set is
for approximate tuning {R1, N1}; the second set is for exact
tuning {R2, N2}.
Approximate tuning with Horseshoe is unique. This
method involves two key elements: (1) increasing the phase
detector frequency and (2) varying boththe R and N divide
values such that the approximate frequency is within a
certain predetermined range. The Horseshoe algorithm
contained in the development system software also allows
placing a constraint on the loop–gain variation that the user
can tolerate.
For example, to tune 1800.270 MHz, the first {R1, N1} data
set could contain divide ratios for the R and N counters of
138.5 and 12,826, respectively. With this data set, the phase
detector is running at about 140 kHz and the approximate
frequency is about 325 Hz from the exact frequency. The
second data set contains R and N divide ratios of 648 and
60,009, respectively. This achieves the exact (target)
frequency of 1800.270 MHz.
The timer must be programmed to determine the interval
that the device is in the approximate–tune mode. For this
example, assume this is 32 fR cycles; thus, bits N21 N20
N19 = 1 0 1 in the first data set. Note that this time interval is
32 cycles of fR, with the phase detector running at about
140 kHz (approximate tune) or about 230
μ
s plus the MCU
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