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參數(shù)資料
| 型號(hào)： | MC145230 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Dual PLL Frequency Synthesizers With DACs and Voltage Multipliers(帶DACs和電壓乘法器的雙PLL頻率合成器) |
| 中文描述： | 雙鎖相環(huán)頻率合成器與DAC和電壓倍增器（帶數(shù)模轉(zhuǎn)換器和電壓乘法器的雙鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 18/71頁 |
| 文件大小： | 906K |
| 代理商： | MC145230 |
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MC145225 MC145230
18
MOTOROLA RF/IF DEVICE DATA
and lock detectors, and the phase/frequency detector output
is enabled to issue an error correction pulse on the next fR
and fV pulses. (Patent issued on this method.)
During standby, data is retained in all registers and any
register may be accessed. When setting or clearing the PLL
Stby bit, other bits in the C register may be changed
simultaneously.
PLL Stby (C0)
When set to 1, this bit places the PLL section of the chip,
which includes the on–chip fin input amp, in the standby
mode for reduced power consumption. PDout is forced to the
floating state. The R and N counters are inhibited from
counting and placed in the low–current mode. The exception
is the R counter’s prescaler when the Mode pin is low. The
R counter’s prescaler remains active along with the fout and
fout pins when PLL is placed in standby (Mode pin = low).
When the Mode pin is low, the fout pin, fout pin, and R
counter’s prescaler are shut down only when Osc Stby bit C2
is set to 1.
When C0 is reset to 0, PLL is taken out of standby in two
steps. All PLL counters and the input amp are enabled. Any
fR and fV signals are inhibited from toggling the associated
phase/frequency detector at this time. Second, when the fR
pulse occurs, the N counter is loaded and the phase/
frequency detector is initialized via both flip–flops being
reset. Immediately after the load, the N and R counters
begin counting down together. At this point, the fR and fV
pulses are enabled to the phase and lock detectors, and the
phase/frequency detector output is enabled to issue an error
correction pulse on the next fR and fV pulses. (Patent issued
on this method.)
During standby, data is retained in all registers, and any
register may be accessed. When setting or clearing the PLL
Stby bit, other bits in the C register may be changed
simultaneously.
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