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參數(shù)資料
| 型號(hào)： | MC145423DT |
| 廠(chǎng)商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 15/15頁(yè) |
| 文件大小： | 0K |
| 描述： | IC TXRX UDLT/ISDN 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 類(lèi)型： | 收發(fā)器 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 管件 |
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MC145423
TELECOMMUNICATIONS
20
PIN DESCRIPTIONS
VSS
Negative Supply (Pin 1)
This is the most negative power pin, and should be
tied to system ground (0 V).
Vref
Voltage Reference Output (Pin 2)
This is the output from the internal reference supply
(mid-supply) and should be bypassed to both VSS and
VDD with 0.1 F capacitors. This pin usually serves
as an analog ground reference for transformer
coupling of the device’s incoming bursts from the line.
No external load should be placed on this pin.
LI
Line Input (Pin 3)
This pin is the input to the demodulator for the
incoming bursts. This input has an internal 240 k
resistor tied to the Vref pin, so an external capacitor or
line transformer may be used to couple the input signal
to the device with no dc offset.
LB
Loopback Low Input (Pin 4)
Master Mode: A low on this pin ties the internal
modulator output to the internal demodulator input,
which loops the entire burst for testing purposes.
During the loopback operation, the LI input is ignored,
and the LO1 and LO2 outputs are driven to equal
voltages. The state of the LB pin is internally latched if
the SE pin is held low. This feature is only active when
the PD input is high.
Slave Mode: When this pin is low and PD is high,
the incoming B channels from the master are burst
back to the master, instead of the Rx B channel input
data. The SDI1 and SDI2 functions operate normally
in this mode, and the BCLK (pin 23) is held low.
Additionally, for both the UDLT-1 and UDLT-2 mode,
when the TONE (pin 18) and loopback functions are
active simultaneously, the loopback function overrides
the TONE function.
VD
Valid Data Output (Pin 5)
A high level on this pin indicates that a valid line
transmission has been demodulated. A valid line
transmission burst is determined by proper
synchronization and the absence of detected bit errors.
VD is a CMOS output and is high impedance when SE
is low.
Master Mode: VD changes state on the rising
edge of MSI, when PD is high. When PD is low, VD
changes state at the end of demodulation of a
transmission burst and does not change again until
three MSI rising edges have occurred, at which time it
goes low, or until the next demodulation of a burst.
Slave Mode: If no transmissions from the master
have been received within the last 250
s, as
determined by an internal oscillator, VD will go low.
SDI1 and SDI2
D Channel Signaling Data Bit Inputs 1 and 2
(Pins 6 and 7)
Master Mode (UDLT-1): These inputs are the
8 kbps serial data inputs in UDLT-1 mode. Data on
these pins is loaded on the rising edge of MSI for
transmission to the slave. The state of these pins is
latched if SE is held low.
Slave Mode (UDLT-1): These inputs are the
8 kbps serial data inputs in UDLT-1 mode. Data on
these pins is loaded on the rising edge of TE1 for
transmission to the master. If no transmissions from
the master are being received and PD is high, data on
these pins will be loaded into the part on an internal
signal. Therefore, data on these pins should be steady
until synchronous communication with the master has
been established, as indicated by the high on VD.
Master Mode (UDLT-2): These inputs are the
16 kbps serial data inputs in UDLT-2 mode. Two bits
should be clocked into each of these inputs between
the rising edges of the MSI frame reference clock. The
first bit of each D channel is clocked into an
intermediate buffer on the first falling edge of the
SDCLK following the rising edge of MSI. The second
bit of each D channel is clocked in on the next
negative transition of the SDCLK. If further SDCLK
negative edges occur, new information is serially
clocked into the buffer replacing the previous data,
one bit at a time. Buffered D channel bits are burst to
the slave on the next rising edge of the MSI frame
reference clock. The state of these pins is latched if SE
is held low.
Slave Mode (UDLT-2): These inputs are the
16 kbps serial data inputs in UDLT-2 mode. The D
channel data bits are clocked in serially on the
negative edge of the 16 kbps SDCLK output pin.
TELECOMMUNICATIONS
17
MC145423
17
EN1-TE1
Input
TE1 8 kHz
TE1 8 kHs
TE1 8 kHz
18
MSI/TONE
Input
MSI 8 kHz
19
CCI/
XTALin
Input
CCI 2.048 MHz
20
TDC-RDC/
XTALout
Input
TDC-RDC
Data Clk
TDC-RDC
Data Clk
TDC-RDC
Data Clk
TDC-RDC
Data Clk
TDC-RDC
Data Clk
21
LI SENS/
2.048 MHz
Input
Digital In
LI Sensitivity
Digital In
LI Sensitivity
Digital In
LI Sensitivity
Digital In
LI Sensitivity
Digital In
LI Sensitivity
22
RE1/
CLKOUT
Input
RE1 8 kHz
23
RE2/
BCLK
Don’t Care High Impedance High Impedance High Impedance High Impedance High Impedance
24
Rx
Input
64 kbps Data In
Don’t Care
25
LO2
Output
Modulator Out
LO2 = LO1
No Effect
LO2 = LO1
26
LO1
Output
Modulator Out
LO1 = LO2
No Effect
LO1 = LO2
27
MASTER/
SLAVE
Input
00000
28
VDD
Power
+V+V+V+V+V
MC145423 UDLT-3 PIN STATES FOR UDLT-1 MASTER MODE (continued)
MC145423
UDLT-1 Master Mode
Powered-Up
UDLT-1 Master Mode
Powered-Down
Pin
No.
Pin
Name
In/out
Normal
LB Low
SE Low
Normal
SE Low
MC145423 UDLT-3 PIN STATES FOR UDLT-2 SLAVE MODE
MC145423
UDLT-2 Slave Mode
Powered-Up
UDLT-2 Slave Mode
Powered-Down
TONE = 0, Off
TONE = 1, On
Pin
No.
Pin
Name
In/out
Normal
LB Low
No Valid
Burst Rec’d
Valid
Burst Rec’d
No Valid
Burst Rec’d
Valid
Burst Rec’d
1VSS
Power
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
2Vref
Analog
Ref
AGND
VDD/2
AGND
VDD/2
AGND
VDD/2
AGND
VDD/2
AGND
VDD/2
AGND
VDD/2
3
LI
Input
Analog In
4LB
Input
1
0
Don’t Care
5
VD
Output
Digital Out
VD = 0
VD = 1
VD = 0
VD = 1
6
SDI1
Input
16 kbps
Data In
16 kbps
Data In
Don’t Care
7
SDI2
Input
16 kbps
Data In
16 kbps
Data In
Don’t Care
8FRAME
10/20
Input
111111
9
SDCLK
Output
16 kHz
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Go to: www.freescale.com
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