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參數(shù)資料
| 型號： | MC145423DT |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX UDLT/ISDN 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 類型： | 收發(fā)器 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 管件 |
MC145423
TELECOMMUNICATIONS
22
250
s have elapsed without a burst from the master
being successfully demodulated. This allows the slave
device to self power-up and power-down in demand
powered loop systems. When held low, the device
powers down and the only active circuitry, is that
which is necessary for the demodulation of data. When
held high, the device is powered up and transmits
normally in response to received bursts from the
master.
MOD TRI/SQ
Modulation Select (Pin 14)
A logic low (0 V) on this pin selects the MDPSK
modulation which has a slew controlled voltage output
for reduced EMI/RFI. This output looks like a triangle
waveform that is modulated with different angles for
the peaks. A logic high (VDD) on this pin, selects
square wave output for maximum power to the line.
Tx
Transmit Data Output (Pin 15)
Master Mode (UDLT-1): This pin is high
impedance when TE1 is low. When TE1 is high, this
pin presents new 8-bit B channel data on rising edges
of TDC-RDC.
Slave Mode (UDLT-1): B channel data is output
on this pin on the rising edge of BCLK, while TE1 is
high. This pin is high impedance when TE1 is low.
Master Mode (UDLT-2): This pin is high
impedance when both TE1 and TE2 are low. This pin
serves as an output for B channel information received
from the slave device. The B channel data is under
control of TE1 and TE2 and TDC-RDC.
Slave Mode (UDLT-2): This pin is an output for
the B channel data received from the master.
B channel 1 data is output on the first eight cycles of
the BCLK output when EN1 is high. B channel 2 data
is output on the next eight cycles of the BCLK, when
EN2 is high. B channel data bits are clocked out on the
rising edge of the BCLK output pin.
EN2-TE2/SIE/B1B2
B Channel 2 Enable Output or
Signal Insert Enable (Pin 16)
Master Mode (SIE UDLT-1): In this mode, this
pin functions as SIE. When held high, this pin causes
signal bit 2, as received from the slave, to be inserted
into the LSB of the outgoing PCM word at the Tx pin.
The SDI2 pin will be ignored, and in its place, the LSB
of the incoming word at the Rx pin will be transmitted
to the slave. The PCM word to the slave will have LSB
forced low in this mode. In this manner, signal bit 2 to/
from the slave UDLT is inserted into the PCM words
the master sends and receives from the backplane, for
routing through the PABX for simultaneous voice/data
communication. The state of this pin is internally
latched if the SE pin is brought and held low.
Slave Mode (UDLT-1): In this mode, this pin is
an input and selects the timeslot used for transferring
the receive data word. When this pin is low, the device
uses the RE1 pin timing the same as the MC145426
UDLT-1 slave. When this pin is a logic 1, the receive
word is latched in during the TE1 timeslot,
simultaneously with the transmit word transfer. The
RE1 pin timing is not affected by this selection.
Master Mode (EN2-TE2 UDLT-2): In this mode,
this pin functions as EN2-TE2. This pin, along with
TE1 pin-17 control the output of data for their
respective B-channel on the Tx output pin. When both
TE1 and TE2 are low, the Tx pin is high impedance.
The rising edge of the respective enable produces the
first bit of the selected B-channel data on the Tx pin.
Internal circuitry then scans for the next negative
transition of the TDC-RDC clock. Following this
event, the next seven bits of the selected B-channel
data are output on the next seven rising edges of the
TDC-RDC data clock. When TE1 and TE2 are high
simultaneously, data on the Tx pin is undefined. TE1
and TE2 should be approximately leading-edge
aligned with the TDC-RDC data clock. To keep the Tx
pin out of the high impedance state, these enable lines
should be high while the respective B channel data is
being output.
Slave Mode (EN2-TE2 UDLT-2): Functioning as
EN2-TE2, this pin is an output and serves as an 8 kHz
enable signal for the input and output of the B channel
2 data. While EN2 is high, B channel 2 data is clocked
out on the Tx pin on the eight rising edges of the
BCLK. During this same time, B channel 2 input data
is clocked in on the Rx pin, on the eight falling edges
of the BCLK.
EN1-TE1
B Channel 1 Enable Output (Pin 17)
This pin is the logical inverse of EN2-TE2, and
serves to control B channel 1 data. See the above pin
description for more information. EN1 serves as the
slave device’s 8 kHz frame reference signal. The VD
TELECOMMUNICATIONS
23
MC145423
pin is also updated on the rising edge of the EN1
signal.
MSI/TONE
Master Sync Input or Tone Enable Input
(Pin 18)
Master Mode (MSI): This pin is the master 8 kHz
frame reference input. The rising edge of MSI loads
B and D channel data, which had been input during the
previous frame, into the modulator section of the
device, and initiates the outbound burst onto the
twisted pair cable. The rising edge of MSI also
initiates the buffering of the B and D channel data
demodulated during the previous frame. MSI should
be approximately leading edge aligned with the TDC-
RDC data clock input signal.
Slave Mode (TONE): A high on this pin causes a
500 Hz square wave PCM tone to be inserted in place
of the demodulated data. This feature allows the
designer to provide audio feedback for telset keyboard
depressions.
CCI/XTALin
Convert Clock Input or Crystal Input (Pin 19)
Master Mode (CCI UDLT-1): A 2.048 MHz
clock signal should be applied to this pin. This signal
is used for internal sequencing and control. This signal
should be frequency and phase coherent with MSI for
optimum performance.
Slave Mode (XTALin UDLT-1): A 4.096 MHz
crystal is tied between this pin and XTALout (pin 20).
A 10 M
resistor across this pin and XTALout and
25 pF capacitors from this pin and XTALout to VSS
are required for stability and to ensure start-up. This
pin may be driven from an external source. XTALout
should be left open if an external signal is used on this
input.
Master Mode (CCI UDLT-2): An 8.192 MHz
clock should be supplied to this input. The 8.192 MHz
input should be 50% duty cycle. This signal may free
run with respect to all other clocks without
performance degradation.
Slave Mode (XTALin UDLT-2): Normally, an
8.192 MHz crystal is tied between this pin and the
XTALout (pin 20). A 10 M resistor between
XTALin and XTALout and 25 pF capacitors from
XTALin and XTALout to VSS are required to ensure
stability and start-up. XTALin may also be driven with
an external 8.192 MHz signal if a crystal is not
desired. XTALout should be left open if an external
signal is used on this input.
TDC-RDC/Xtalout
Transmit and Receive Data Clock or Crystal
Output (Pin 20)
Master Mode (TDC-RDC): This input is the
transmit and receive data clock for the B channel data.
Output data changes state on the rising edge of this
signal, and input data is read on the falling edges of
this signal. TDC-RDC should be roughly leading edge
aligned with MSI.
Slave Mode (XTALout): This pin is the crystal
out pin. It is capable of driving one external CMOS
input and 15 pF of additional capacitance. See pin
description for XTALin (pin 19).
LI SENS/2.048 MHz
Line Input Sensitivity or 2.048 MHz Output
(Pin 21)
Master Mode: By applying a logic 1 on this pin,
the sensitivity of LI is reduced by 15 dB. This reduces
the effects of crosstalk, and false detects that would be
picked up and demodulated when the LI pin is
connected to an open loop.
Slave Mode: This pin outputs a 2.048 MHz signal
for use with a PCM codec-filter. All other device
clocks are generated from the rising edge of this clock.
The 8 kHz enables are derived by dividing this
2.048 MHz clock by a nominal ratio of 256. Phase
synchronization to the master UDLT’s burst is
achieved by dividing this clock by the ratios of either
255, 256, or 257.
RE1/CLKOUT
Receive Data Enable 1 Input or Clock Output
(Pin 22)
Master Mode (RE1 UDLT-1): A rising edge on
this pin will enable data on the Rx pin to be loaded
into the receive data register on the next eight falling
edges of the TDC-RDC data clock. RE1 and TDC-
RDC should be approximately leading edge aligned.
Slave Mode (RE1 UDLT-1): This B series
CMOS output is the inverse of TE1 (see TE1 pin
description).
Master Mode (RE1 UDLT-2): This input along
with RE2 (pin 23) control the input of B channel data
on the Rx pin. The rising edge of the respective enable
signal causes the device to load the selected receive
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Go to: www.freescale.com
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